Development and validation of a hierarchical memory model incorporating CPU- and memory-operation overlap

Proceedings of the 1st International Workshop on Software and Performance, WOSP 1998

Volumn , Issue , 1998, Pages 152-163

  Luo, Yong ^a   Lubeck, Olaf M ^a   Wasserman, Harvey ^a   Bassetti, Federico ^a   Cameron, Kirk W ^a  

^a LOS ALAMOS NATIONAL LABORATORY   (United States)

Author keywords

Cache; Computer architecture; Memory subsystem; Microprocessor; Performance evaluation

Indexed keywords

COMPUTER ARCHITECTURE; MEMORY ARCHITECTURE; MICROPROCESSOR CHIPS; SUPERCOMPUTERS;

CACHE; CYCLES PER INSTRUCTIONS; HIERARCHICAL MEMORY MODELS; MEMORY HIERARCHY; MEMORY OPERATIONS; MEMORY SUBSYSTEMS; PERFORMANCE EVALUATION; PROCESSOR EXECUTION;

CACHE MEMORY;

EID: 84997243719     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/287318.287349     Document Type: Conference Paper

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