METERG: Measurement-based end-to-end performance estimation technique in QoS- capable multiprocessors

Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS

Volumn 2006, Issue , 2006, Pages 135-143

  Lee, Jae W ^a   Asanović, Krste ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MEASUREMENT-BASED END-TO-END PERFORMANCE ESTIMATION; MULTIPROCESSOR SIMULATOR; OPERATION MODES; UNIPROCESSOR SYSTEM;

COMPUTER SIMULATION; MULTIPROCESSING PROGRAMS; OPTIMIZATION; QUALITY OF SERVICE; REAL TIME SYSTEMS;

PARAMETER ESTIMATION;

EID: 33749646951     PISSN: 15453421     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RTAS.2006.29     Document Type: Conference Paper

References (26)

1. C. Akinlar and S. Mukherjee. Bandwidth Guarantee in a Distributed Multimedia File System Using Network Attached Autonomous Disks. In IEEE Real Time Technology and Applications Symposium, 2000.
2. A. Anantaraman, K. Seth, K. Patil, E. Rotenberg, and F. Mueller. Virtual Simple Architecture (VISA): Exceeding the Complexity Limit in Safe Real-time Systems. In ISCA'03: Proceedings of the 30th Annual International Symposium on Computer Architecture, pages 350-361, New York, NY, USA, 2003. ACM Press.
3. R. Arnold, F. Mueller, D. B. Whalley, and M. Harmon. Bounding Worst-case Instruction Cache Performance. In Proceedings of the Real-Time Systems Symposium (RTSS), Dec. 1994.
4. B. Case. First Trimedia Chip Boards PCI Bus. Microprocessor Report, Nov 1995.
5. F. J. Cazorla, A. Ramírez, M. Valero, P. M. W. Knijnenburg, R. Sakellariou, and E. Fernández. QoS for High-Performance SMT Processors in Embedded Systems. IEEE Micro, 24(4):24-31, 2004.
6. A. El-Haj-Mahmoud and E. Rotenberg. Safely Exploiting Multithreaded Processors to Tolerate Memory Latency in Real-time Systems. In CASES '04: Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems, pages 2-13, New York, NY, USA, 2004. ACM Press.
7. C. A. Healy, R. D. Arnold, F. Mueller, M. G. Harmon, and D. B. Walley. Bounding Pipeline and Instruction Cache Performance. IEEE Trans. Comput., 48(1):53-70, 1999.
8. Intel Corp. Paragon XP/S Product Overview. Intel Corporation, 1991.
9. R. Iyer. CQoS: a Framework for Enabling QoS in Shared Caches of CMP Platforms. In ICS '04: Proceedings of the 18th annual International Conference on Supercomputing, pages 257-266, New York, NY, USA, 2004. ACM Press.
10. Jae H. Kim and Andrew A. Chien. Rotating Combined Queueing (RCQ): Bandwidth and Latency Guarantees in Low-cost, High-performance Networks. In ISCA '96: Proceedings of the 23rd Annual International Symposium on Computer Architecture, pages 226-236, New York, NY, USA, 1996. ACM Press.
11. R. Jain, C. J. Hughes, and S. V. Adve. Soft Real- Time Scheduling on Simultaneous Multithreaded Processors. In IEEE Real-Time Systems Symposium, 2002.
12. K. Lawton. Bochs: The cross-platform IA-32 emulator. http://bochs. sourceforge.net.
13. R. N. Kalla, B. Sinharoy, and J. M. Tendier. IBM Power5 Chip: A Dual-Core Multithreaded Processor. IEEE Micro, 24(2):40-47, 2004.
14. K. Krewell. ARM Opens Up to SMP. Microprocessor Report, May 2004.
15. Larry L. Peterson and Bruce S. Davie. Computer Networks: a Systems Approach, 2nd Ed. Morgan Kaufmann Publishers Inc., San Francisco, CA, USA, 2000.
16. S. Lim, Y. Bae, G. Jang, B. Rhee, S. Min, C. Park, H. Shin, K. Park, and C. Kim. An Accurate Worst Case Timing Analysis Technique for RISC Processors. In Proceedings of the 15th IEEE Real-Time Systems Symposium (RTSS), pages 97-108, 1994.
17. C. L. Liu and J. W. Layland. Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment. Journal of the ACM, 20(1):46-61, 1973.
18. N. Kushman. Performance Nonmonotonicities: A Case Study of the UltraSPARC Processor. Technical Report MIT/LCS/TR-782, 1998.
19. Sathish Gopalakrishnan and Lui Sha and Marco Caccamo. Hard Real-Time Communication in Bus-Based Networks. In Proceedings of the 25th IEEE Real-Time Systems Symposium (RTSS 2004), 5-8 December 2004, Lisbon, Portugal, pages 405-414. IEEE Computer Society, 2004.
20. M. Shalan and V. J. Mooney. A Dynamic Memory Management Unit for Embedded Real-time System-on-a-chip. In CASES '00: Proceedings of the 2000 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, pages 180-186, New York, NY, USA, 2000. ACM Press.
21. F. Stappert, A. Ermedahl, and J. Engblom. Efficient longest executable path search for programs with complex flows and pipeline effects. In CASES '01: Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems, pages 132-140, New York, NY, USA, 2001. ACM Press.
22. J. Sun and J. Liu. Synchronization Protocols in Distributed Real-Time Systems. In ICDCS '96: Proceedings of the 16th International Conference on Distributed Computing Systems (ICDCS '96), Washington, DC, USA, 1996. IEEE Computer Society.
23. Thomas Lundqvist and Per Stenstrom. Timing Anomalies in Dynamically Scheduled Microprocessors. In RTSS '99: Proceedings of the 20th IEEE Real-Time Systems Symposium, Washington, DC, USA, 1999. IEEE Computer Society.
24. J. Wu and S. Brandt. Storage Access Support for Soft RealTime Applications. In IEEE Real Time Technology and Applications Symposium, 2004.
25. K. H. Yum, E. J. Kim, C. R. Das, and A. S. Vaidya. MediaWorm: A QoS Capable Router Architecture for Clusters. IEEE Trans. Parallel Distrib. Syst., 13(12): 1261-1274, 2002.
26. N. Zhang, A. Burns, and M. Nicholson. Pipelined Processors and Worst Case Execution Times. Technical Report University of York-CS 198, 1993.