System-level reliability modeling for MPSoCs

Embedded Systems Week 2010 - Proceedings of the 8th IEEE/ACM/IFIP International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CODES+ISSS'2010

Volumn , Issue , 2010, Pages 297-306

  Xiang, Yun ^a   Chantem, Thidapat ^b   Dick, Robert P ^a   Hu, X Sharon ^b   Shang, Li ^c  

^a The Department of Civil and Environmental Engineering   (United States)

^b UNIVERSITY OF NOTRE DAME   (United States)

^c UNIVERSITY OF COLORADO   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AVERAGE ERRORS; DESIGN AND OPTIMIZATION; EXTREME VALUE DISTRIBUTIONS; FAULT DISTRIBUTION; MEAN TIME TO FAILURE; MODELING TECHNIQUE; MONTE CARLO TECHNIQUES; MULTIPROCESSOR-SYSTEM; ORDERS OF MAGNITUDE; PHYSICAL EFFECTS; PHYSICAL PROCESS; REDUNDANCY SCHEME; RELIABILITY MODELING; SIGNIFICANT IMPACTS; SIMULATION TIME; STATIC AND DYNAMIC; STATISTICAL RELIABILITY; STRESS MIGRATION; SYSTEM LEVELS; SYSTEM-LEVEL MODELS; TIME-DEPENDENT DIELECTRIC BREAKDOWN; MULTI-PROCESSORS; PERFORMANCE; SYSTEMS ON CHIPS;

HIERARCHICAL SYSTEMS; MONTE CARLO METHODS; REDUNDANCY; MICROPROCESSOR CHIPS; MODELS;

EMBEDDED SYSTEMS; REDUNDANCY;

EID: 78650660443     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1878961.1879013     Document Type: Conference Paper

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