Performance optimal processor throttling under thermal constraints

CASES'07: Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems

Volumn , Issue , 2007, Pages 257-266

  Rao, Ravishankar ^a   Vrudhula, Sarma ^a  

^a ARIZONA STATE UNIVERSITY   (United States)

Author keywords

Leakage dependence on temperature; Power; Thermal management; Thermal model; Throttling

Indexed keywords

APPROXIMATION THEORY; DYNAMIC PROGRAMMING; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; OPTIMAL CONTROL SYSTEMS; SPEED CONTROL; TEMPERATURE CONTROL;

LEAKAGE DEPENDENCE ON TEMPERATURE; OPTIMAL CONTROL POLICY; THERMAL MODELS; THROTTLING;

PROGRAM PROCESSORS;

EID: 38849163446     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1289881.1289925     Document Type: Conference Paper

References (29)

1. D. Brooks and M. Martonosi, "Dynamic thermal management for high-performance microprocessors," in Intl' Symp. High Speed Computer Arch. (HPCA), 2001, pp. 171-182.
2. W. Huang, M. R. Stan, K. Skadron, K. Sankaranarayanan, and S. Ghosh, "Hotspot: A compact thermal modeling method for cmos vlsi systems," IEEE Trans. VLSI Sys., vol. 14, no. 5, pp. 501-513, May 2006.
3. C. Isci, A. Buyuktosunoglu, C.-Y. Cher, P. Bose, and M. Martonosi, "An analysis of efficient multi-core global power management policies: Maximizing performance for a given power budget," in Proc. Intl' Symp. Microarch (MICRO), 2006, pp. 347-358.
4. J. Donald and M. Martonosi, "Techniques for multicore thermal management: Classification and new exploration," in Proc. Intl' Symp. Comp. Arch. (ISCA), 2006.
5. A. Cohen, F. Finkelstein, A. Mendelson, R. Ronen, and D. Rudoy, "On estimating optimal performance of cpu dynamic thermal management," IEEE Computer Architecture Letters, vol. 2, no. 1, pp. 6-6, 2003.
6. S. Heo, K. Barr, and K. Asanovic, "Reducing power density through, activity migration," in Proc. Intl' Symp. Low Power Electronics and Design (ISLPED), 2003, pp. 217-222.
7. J. Srinivasan and. S. V. Adve, "Predictive dynamic thermal management for multimedia applications," in Proc. Intl' Conf. Supercomputing (ICS), 2003, pp. 109-120.
8. W. Liao, L. He, and K. M. Lepak, 'Temperature and supply voltage aware performance and power modeling at microarchitecture level," IEEE Trans. Computer-Aided Design, vol. 24, no. 7, pp. 1042-1053, July 2005.
9. R. Rao, S. Vrudhula, C. Chakrabarti, and N. Chang, "An optimal analytical solution for processor speed control with, thermal constraints," in Proc. Intl' Symp. Low Power Electronics and Design (ISLPED), October 2006, pp. 292-297.
10. N. Bansal, T. Kimbrel, and K. Pruhs, "Speed scaling to manage energy and temperature," J. ACM, vol. 54, no. 1, 2007.
11. R. Mukherjee and S. O. Memik, "Physical aware frequency selection for dynamic thermal management in multi-core systems," in Proc. Intl' Conf. Computer Aided Design (ICCAD), 2006, pp. 547-552.
12. H. Su, F. Liu, A. Devgan, E. Acar, and S. Nassif, "Full chip leakage estimation considering power supply and temperature variations," in Proc. Intl' Symp. Low Power Electronics and Design (ISLPED), 2003, pp. 78-83.
13. A. Dhodapkar, C. H. Lim, G. Cai, and W. R. Daasch, "TEMPEST: A thermal-enabled multi-model power/performance simulator," in Proc. Workshop on Power-Aware Computer Systems, November 2000.
14. W. Lee, K. Patel, and. M. Pedram, "Dynamic thermal management for mpeg-2 decoding," in Proc. Intl' Symp. Low Power Electronics and Design (ISLPED), 2006, pp. 316-321.
15. Y. Li, D. Parikh, Y. Zhang, K. Sankaranarayanan, M. Stan, and K. Skadron, "State-preserving vs. non-state-preserving leakage control in caches," in Proc. Design Automation and Test in Europe Conf. (DATE), 2004, pp. 22-27.
16. H. Aydin, R. Melhem, D. Mosse, and P. Mejia-Alvarez, "Determining optimal processor speeds for periodic real-time tasks with different power characteristics," in Proc. Euromicro Conf. Real-Time Sys., 2001, pp. 225-232.
17. T. Ishihara and H. Yasuura, "Voltage scheduling problem, for dynamically variable voltage processors," in Proc. Intl' Symp. Low Power Electronics and Design (ISLPED), 1998, pp. 197-202.
18. J. R. Lorch and A. J. Smith, "PACE: A new approach to dynamic voltage scaling," IEEE Trans. Computers, vol. 53, no. 7, pp. 856-869, July 2004.
19. P. Pillai and K. G. Shin, "Real-time dynamic voltage scaling for low-power embedded operating systems," in Proc. SIGOPS. ACM Press, 2001, pp. 89-102.
20. R. Jejurikar, C. Pereira, and R. Gupta, "Leakage aware dynamic voltage scaling for real-time embedded systems," in Proc. Design Automation Conf. (DAC), 2004, pp. 275-280.
21. F. Yao, A. Demers, and S. Shenker, "A scheduling model for reduced CPU energy," in Proc. Symp. Foundations of Computer Science, 1995, pp. 374-382.
22. J. Luo and N. K. Jha, "Battery-aware static scheduling for distributed real-time embedded systems," in DAC '01: Proc. Design Automation Conference. ACM Press, 2001, pp. 444-449.
23. D. Rakhmatov and S. Vrudhula, "Energy management for battery-powered embedded, systems," Trans. on Embedded Computing Sys., vol. 2, no. 3, pp. 277-324, 2003.
24. K. Skadron, T. Abdelzaher, and M. R. Stan, "Control-theoretic techniques and thermal-RC modeling for accurate and localized dynamic thermal management," in Proc. Intl' Symp. High Perf. Comp. Arch. (HPCA), 2002, pp. 17-28.
25. R. Rao, S. Vrudhula, and C. Chakrabarti, "Throughput of multi-core processors under thermal constraints," in Proc. Intl' Symp. Low Power Electronics and Design (ISLPED), August 2007.
26. Intel Pentium 4 Processor 6x1 Sequence: Datasheet, Intel Corp., January 2006.
27. CPU Thermal Management: Application Note, Advanced Micro Devices. [Online]. Available: http://www.amd.com/epd/processors/6.32bitproc/xl8448/18448. pdf
28. D. S. Naidu, Optimal Control Systems. CRC Press, 2002.
29. AMD Athlon 64 Processor Power and Thermal Data Sheet, Advanced Micro Devices, August 2004.