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Volumn , Issue , 2007, Pages

A low-power low-swing single-ended multi-port SRAM

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DATA ACQUISITION; SPURIOUS SIGNAL NOISE;

EID: 34648831082     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VDAT.2007.373203     Document Type: Conference Paper
Times cited : (15)

References (9)
  • 2
    • 20444436009 scopus 로고    scopus 로고
    • A Low-Power SRAM Using Hierachical Bitline and Local Sense Amplifiers
    • Jun
    • Byung-Do Yang and Lee-Sup Kim, "A Low-Power SRAM Using Hierachical Bitline and Local Sense Amplifiers," IEEE J. Solid-State Circuits, vol 40, Jun. 2005, pp. 1366-1376.
    • (2005) IEEE J. Solid-State Circuits , vol.40 , pp. 1366-1376
    • Yang, B.1    Kim, L.2
  • 3
    • 2942691849 scopus 로고    scopus 로고
    • Kouichi Kanda, Hattori Sadaaki, and Takayasu Sakurai, 90% Write Power-Saving SRAM Using Sense-Amplifying Memory Cell, IEEE J. Solid-State Circuits, 39, Jun, 2004, pp. 927-933.
    • Kouichi Kanda, Hattori Sadaaki, and Takayasu Sakurai, "90% Write Power-Saving SRAM Using Sense-Amplifying Memory Cell," IEEE J. Solid-State Circuits, vol. 39, Jun, 2004, pp. 927-933.
  • 4
    • 0035472467 scopus 로고    scopus 로고
    • A Low-Power High-Performance Current-Mode Multiport SRAM
    • Oct
    • Muhammad M. Khellah, and Mohamed I. Elmasry, "A Low-Power High-Performance Current-Mode Multiport SRAM," IEEE Transaction on VLSI Systems, vol. 9, Oct. 2001, pp. 590-597.
    • (2001) IEEE Transaction on VLSI Systems , vol.9 , pp. 590-597
    • Khellah, M.M.1    Elmasry, M.I.2
  • 5
    • 0033908207 scopus 로고    scopus 로고
    • Low-Power Embedded SRAM with the Current-Mode Write Technique
    • Jan
    • Jinn-Shyan Wang, Wayne Tseng, and Huang-Yu Li, "Low-Power Embedded SRAM with the Current-Mode Write Technique," IEEE J. Solid-State Circuits, vol. 35, Jan. 2000, pp. 119-124.
    • (2000) IEEE J. Solid-State Circuits , vol.35 , pp. 119-124
    • Wang, J.1    Tseng, W.2    Li, H.3
  • 6
    • 34648844460 scopus 로고    scopus 로고
    • Distributed Data-Retention Power Gating Techniques for Column and Row Co-Controlled Embedded SRAM
    • Chung-Hsien Hua, Tung-Shuan Cheng, and Wei Hwang, "Distributed Data-Retention Power Gating Techniques for Column and Row Co-Controlled Embedded SRAM," IEEE MTDT'05, 2005.
    • (2005) IEEE MTDT'05
    • Hua, C.1    Cheng, T.2    Hwang, W.3
  • 7
    • 34648847590 scopus 로고    scopus 로고
    • Value-Conscious Cache: Simple Technique for Reducing Cache Access Power
    • Yen-Jen Chang, Chia-Lin Yang, and Feipei Lai, "Value-Conscious Cache: Simple Technique for Reducing Cache Access Power", IEEE DATE'04, 2004.
    • (2004) IEEE DATE'04
    • Chang, Y.1    Yang, C.2    Lai, F.3
  • 8
    • 0033908206 scopus 로고    scopus 로고
    • Single-Ended SRAM with High Test Converage and Short Test Time
    • Jan
    • Chua-Chin Wang, Chi-Feng Wu, Rain-Ten Hwang, and Chia-Hsiuang Kao, "Single-Ended SRAM with High Test Converage and Short Test Time," IEEE J. Solid-State Circuits, vol. 35, Jan. 2000, pp. 114-118.
    • (2000) IEEE J. Solid-State Circuits , vol.35 , pp. 114-118
    • Wang, C.1    Wu, C.2    Hwang, R.3    Kao, C.4
  • 9
    • 0029713702 scopus 로고    scopus 로고
    • Demonstration of ST SRAM And 6T Dual-Port RAM Cell Arrays
    • Jun
    • Hiep Tran, "Demonstration of ST SRAM And 6T Dual-Port RAM Cell Arrays," IEEE 1996 Symposium on VLSI Circuits, Jun. 1996, pp. 68-69.
    • (1996) IEEE 1996 Symposium on VLSI Circuits , pp. 68-69
    • Tran, H.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.