Asymmetrical write-assist for single-ended SRAM operation

Proceedings - IEEE International SOC Conference, SOCC 2009

Volumn , Issue , 2009, Pages 101-104

  Lin, Jihi Yu ^a   Tu, Ming Hsien ^a   Tsai, Ming Chien ^a   Jou, Shyh Jye ^a   Chuang, Ching Te ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

90NM CMOS; AVERAGE POWER; OPERATION FREQUENCY; OPERATION SPEED; POSITIVE FEEDBACK; SINGLE-ENDED; SRAM CELL; STATIC NOISE MARGIN; WRITE MARGIN;

CMOS INTEGRATED CIRCUITS; FEEDBACK; PROGRAMMABLE LOGIC CONTROLLERS;

STATIC RANDOM ACCESS STORAGE;

EID: 77949609975     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOCCON.2009.5398086     Document Type: Conference Paper

References (6)

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2. K. Kim, J. J. Kim, and C.T. Chuang, "Asymmetrical SRAM Cells with Enhanced Read and Write Margins," Proc. VLSITSA, April, 2007, pp. 162-163.
3. R. F. Hobson, "A New Single-Ended SRAM Cell with Write-Assist, " IEEE Transactions on VLSI, Vol. 15, Issue 2, Feb. 2007, pp. 173-181.
4. A. Sil, S. Ghosh, and M. Bayoumi, "A Novel 90nm 8T SRAM Cell With Enhanced Stability," Proc. ICICDT, May, 2007, pp. 1-4.
5. B. H. Calhoun and A.P. Chandrakasan, "Static Noise Margin Variation for Sub-threshold SRAM in 65-nm CMOS," IEEE Journal of Solid-State Circuits, Vol. 41, Issue 7, July, 2006, pp.1673-1679.
6. H. Noguchi, S. Okumura, Y. Iguchi, H. Fujiwara, Y. Morita, K. Nii, H. kawaguchi, and M. Yoshimoto, "Which is the Best Dual-Port SRAM in 45-nm Process Technology? - 8T, 10T Single End, and 10T Differential -," Proc. ICICDT, June 2007, pp.55-58.