A new single-ended SRAM cell with write-assist

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 15, Issue 2, 2007, Pages 173-181

  Hobson, Richard F ^a  

^a SIMON FRASER UNIVERSITY   (Canada)

Author keywords

Leakage powered bit lines; Low leakage static random access memory (SRAM); Low power memory; Single ended 6T SRAM cell

Indexed keywords

ENERGY DISSIPATION; INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS; MOS DEVICES;

LEAKAGE POWERED BIT LINES; LOW LEAKAGE STATIC RANDOM ACCESS MEMORY (SRAM); LOW POWER MEMORY; SINGLE-ENDED 6T SRAM CELL;

STATIC RANDOM ACCESS STORAGE;

EID: 34047128129     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2007.893580     Document Type: Article

References (22)

1. R. W. Mann et al., "Ultralow-power SRAM technology," IBM J. Res. Dev., vol. 47, no. 5/6, pp. 553-566, Sep./Nov. 2003.
2. T. B. Hook, M. Breitwisch, J. Brown, P. Cottrell, D. Hoyniak, C. Lam, and R. Mann, "Noise margin and leakage in ultra-low leakage SRAM cell design," IEEE Trans. Electron Devices, vol. 49, no. 8, pp. 1499-1501, Aug. 2002.
3. F. Hamzaoglu, Y. Ye, A. Keshavorzi, K. Zhang, S. Narendra, S. Borkar, M. Stan, and V. De, "Analysis of dual-Vt SRAM cells with full-swing single-ended bit line sensing for on-chip cache," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 10, no. 2, pp. 91-95, Apr. 2002.
4. N. Azizi, A. Moshovos, and F. Najm, "Low-leakage asymmetric-cell SRAM." in Proc. ISLPED, 2002, pp. 48-51.
5. H. Tran, "Demonstration of 5T SRAM and 6T dual-port RAM cell arrays," in Proc. lEEE Symp. VLSI Circuits, 1996, pp. 68-69.
6. C. Wang, C. Wu, R. Hwang, and C. Kao, "Single-ended SRAM with high test coverage and short test time," IEEE J. Solid-State Circuits, vol. 35, no. 1, pp. 114-118, Jan. 2000.
7. I. Carlson, "Design and evaluation of high density 5T SRAM cache for advanced microprocessors." M.S. thesis, Dept. Electr. Eng., Linkoping Univ., Linkoping, Sweden, 2004.
8. R. Hobson, "A compact multiport static random access memory cell," U.S. Patent No. 5 754 468, May 19, 1998.
9. UMC, Taiwan, "SoC solutions." 2005 [Online]. Available: www.umc.com/English/process/b.asp
10. R. Hobson, "Write-Assisted SRAM Bit Cell," U.S. Patent No. 6 804 143, Oct. 12, 2004.
11. F. Hamzaoglu, Y. Ye, A. Keshavarzi, K. Zhang, S. Narendra, S. Borkar, M. Stan, and V. De, "Dual-Vt SRAM cells with full-swing single-ended bit line sensing for high-performance on-chip cache in 0.13 μm technology generation," in Proc. ISLPED, 2000, pp. 15-19.
12. H. Kondoh, H. Yamanaka, M. Ishiwaki, Y. Matsuda, and M. Nakaya, "An efficient self-timed queue architecture," in Proc. IEEE CICC, 1994, pp. 637-640.
13. K. Mai, T. Mori, B. S. Amrutur, R. Ho, B. Wilburn, M. Horowitz, I. Fukushi, T. Izawa, and S. Mitarai, "Low-power SRAM design using half-swing pulse-mode techniques," IEEE J. Solid-Slate Circuits, vol. 33, no. 11, pp. 1659-1671, Nov. 1998.
14. B. Amrutur and M. Horowitz, "Fast low-power decoders for RAMs," IEEE J. Solid-State Circuits, vol. 36, no. 10, pp. 1506-1515, Oct. 2001.
15. S. Heo, K. Barr, M. Hampton, and K. Asanovic, "Dynamic fine-grain leakage reduction using leakage-biased bitlines," presented at the ISCA-29, Anchorage, AK, May 2002.
16. J. Greason, D. Buehler, J. Kolousek, Y. Ng, K. Sarkez, P. Shay, and A. Waizman, "A 4.5 Megabit, 560 MHz, 4.5 GByte/s high bandwidth SRAM," in Proc. Symp. VLSI Circuits, 1997, pp. 15-16.
17. R. Singh and N. Bhat, "An offset compensation technique for latch type sense amplifiers in high-speed low-power SRAMs." IEEE Tran. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 6, pp. 652-657, Jun. 2004.
18. Y. Chang, F. Lai, and C. Yang, "Zero-aware asymmetric SRAM cell for reducing cache power in writing zero," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 8, pp. 827-836, Aug. 2004.
19. C. Kim, J. Kim, S. Mukhopadhyay, and K. Roy, "A forward body-biased low-leakage SRAM cache: Device, circuit and architecture considerations." IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 3, pp. 349-357, Mar. 2005.
20. A. Moshovos, B. Falsafi, F. Najm, and N. Azizi, "A case for asymmetric-cell cache memories," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 7, pp. 877-881, Jul. 2005.
21. M. Kandemir, M. Irwin, G. Chen, and I. Kolcu, "Compiler-guided leakage optimization for banked scratch-pad memories." IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 10, pp. 1136-1146, Oct. 2005.
22. N. Kim, D. Blaauw, and T. Mudge, "Quantitative analysis and optimization techniques for on-chip cache leakage power," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 10, pp. 1147-1155, Oct. 2005.