SCOPUS 정보 검색 플랫폼

Proceedings 2007 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT

Volumn , Issue , 2007, Pages 242-245

A novel 90nm 8T SRAM cell with enhanced stability

(3) Sil, Abhijit a Ghosh, Soumik a Bayoumi, Magdy a

a University of Louisiana at Lafayette (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARSENIC COMPOUNDS; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUITS; SYSTEM STABILITY; TECHNOLOGY;

CHANNEL LENGTHS; CHANNEL REGIONS; DEVICE GEOMETRIES; DOPANT FLUCTUATIONS; ENHANCED STABILITY; FUTURE TECHNOLOGY; INTEGRATED CIRCUIT (IC) DESIGN; INTERNATIONAL CONFERENCES; READ OPERATIONS; SCALING DOWN; SRAM CELLS; SRAM STABILITY;

STATIC RANDOM ACCESS STORAGE;

EID: 47349130704 PISSN: None EISSN: None Source Type: Conference Proceeding
DOI: 10.1109/ICICDT.2007.4299582 Document Type: Conference Paper

Times cited : (12)

References (7)

1
- 0035308547
- A. Bhavnagarwala, X. Tang, and J. Meindl, The impact of intrinsic device fluctuations on CMOS SRAM cell stability, Solid-State Circuits, IEEE Journal of, 2001, 36, 658-665
- A. Bhavnagarwala, X. Tang, and J. Meindl, "The impact of intrinsic device fluctuations on CMOS SRAM cell stability", Solid-State Circuits, IEEE Journal of, 2001, 36, 658-665

2
- 33746369469
- B. Calhoun and Chandrakasan, A.Static noise margin variation for subthreshold SRAM in 65-nm CMOS, Solid-State Circuits, IEEE Journal of, 2006, 41, 1673-1679
- B. Calhoun and Chandrakasan, "A.Static noise margin variation for subthreshold SRAM in 65-nm CMOS", Solid-State Circuits, IEEE Journal of, 2006, 41, 1673-1679

3
- 34547298101
- Evaluation of differential vs. single-ended sensing and asymmetric cells in 90 nm logic technology for on-chip caches
- 4pp
- Y. Ye, M. Khellah, D. Somasekhar and V. De, "Evaluation of differential vs. single-ended sensing and asymmetric cells in 90 nm logic technology for on-chip caches", Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on, 2006, 4pp.
- (2006) Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
- Ye, Y.¹ Khellah, M.² Somasekhar, D.³ De, V.⁴

4
- 47349090468
- A low leakage and SNM free SRAM cell design in deep sub micron CMOS technology VLSI Design
- S. Jain and P. Agarwal, "A low leakage and SNM free SRAM cell design in deep sub micron CMOS technology VLSI Design", 2006. Held jointly with 5th International Conference on Embedded Systems and Design., 19th International Conference on, 2006, 4pp.
- (2006) Held jointly with 5th International Conference on Embedded Systems and Design., 19th International Conference on , vol.2006
- Jain, S.¹ Agarwal, P.²

5
- 4043144988
- Zero-aware asymmetric SRAM cell for reducing cache power in writing zero
- Y. Chang, F. Lai and C. Yang, "Zero-aware asymmetric SRAM cell for reducing cache power in writing zero", Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 2004 , 12, 827-836
- (2004) Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol.12 , pp. 827-836
- Chang, Y.¹ Lai, F.² Yang, C.³

6
- 33644640188
- VLSI Technology, Digest of Technical Papers. 2005 Symposium on
- L. Chang, D. Fried and J. Hergenrother, "Stable SRAM cell design for the 32 nm node and beyond", VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on, 2005, 128-129
- (2005) Stable SRAM cell design for the 32 nm node and beyond , pp. 128-129
- Chang, L.¹ Fried, D.² Hergenrother, J.³

7
- 0023437909
- E. Seevink and F. List, Static Noise Margin Analysis of MOS SRAM Cells, Solid-State Circuits, IEEE Journal of, 1987, 5, 748-754
- E. Seevink and F. List, "Static Noise Margin Analysis of MOS SRAM Cells", Solid-State Circuits, IEEE Journal of, 1987, 5, 748-754

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