A stable SRAM cell design against simultaneously R/W disturbed accesses

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2006, Pages 11-12

  Suzuki, Toshikazu ^a   Yamauchi, Hiroyuki ^b   Yamagami, Yoshinobu ^a   Satomi, Katsuji ^a   Akamatsu, Hironori ^a  

^a PANASONIC CORPORATION   (Japan)

^b FUKUOKA INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BICMOS TECHNOLOGY;

READ AND WRITE (R/W) DISTURBED ACCESSES; SRAM CELL DESIGN;

STATIC RANDOM ACCESS STORAGE;

EID: 39749191416     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. L. Chang, et al., Symp. VLS I Tech.,2005, p128.
2. K. Takeda, et al., ISSCC, 2005, p478.
3. K. Zhang, et al., ISSCC, 2005, p474.
4. M. Yamaoka, et al., ISSCC, 2005, p480.
5. Y. Kagenishi, et al., Symp. VLSI Cir., 1993, p43