A microcontroller-based PVT control system for A 65nm 72Mb synchronous SRAM

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 53, Issue , 2010, Pages 184-185

  Eid, Sherif T ^a   Whately, Morgan ^a   Krishnegowda, Sandeep ^a  

^a CYPRESS SEMICONDUCTOR   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BODY BIAS; DIE SIZE; DIGITAL SYSTEM; GATE DENSITY; LEAKAGE CONTROL; MEMORY CORE; ON CHIPS; OPERATING MARGINS; PARAMETRIC YIELD; POST-SILICON; POWER DOMAIN; PROCESS VARIATION; REAL TIME; SILICON CMOS; SPEED DISTRIBUTIONS; SPEED IMPROVEMENT; SRAM CHIP; SUB-THRESHOLD LEAKAGE; SUPPLY VOLTAGES; TEST STRUCTURE; VOLTAGE REFERENCE;

ANALOG CIRCUITS; CMOS INTEGRATED CIRCUITS; DIES; DIGITAL CONTROL SYSTEMS; LEAKAGE CURRENTS; MICROCONTROLLERS; SILICON WAFERS; STATIC RANDOM ACCESS STORAGE; TEMPERATURE SENSORS;

CONTROLLERS;

EID: 77952157312     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2010.5433998     Document Type: Conference Paper

References (4)

1. th Monitoring and Body Bias for NMOS and PMOS," ISSCC Dig. Tech. Papers, pp. 384-385, Feb. 2008.
2. H. Yu, et al., "A SRAM Core Architecture with Adaptive Cell Bias Scheme," Dig. Symp. VLSI Circuit, pp. 128-129, Jun. 2006.
3. S. Mukhopadhyay, H. Mahmoodi, K. Roy, "Reduction of parametric failures in sub-100nm SRAM array using body bias," IEEE Trans. On Computer-Aided Design of Integrated Circuits and Systems, vol. 27, pp. 174-183, January 2008.
4. S. Kumar, C. Kim, S. Sapatnekar, "Body Bias Voltage Computations for Process and Temperature Compensation," IEEE Trans. On VLSI Systems, vol. 16, no. 3, pp. 249-262, March 2008.