Activity-sensitive clock tree construction for low power

Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 2002, Pages 279-282

  Chen, Chunhong ^a   Kang, Changjun ^a   Sarrafzadeh, Majid ^b  

^a UNIVERSITY OF WINDSOR   (Canada)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Activity pattern; Clock gating; Clock tree; Low power

Indexed keywords

ALGORITHMS; ELECTRIC NETWORK TOPOLOGY; ELECTRIC POWER SUPPLIES TO APPARATUS; INTERCONNECTION NETWORKS; LOGIC GATES; OPTIMIZATION; TIMING CIRCUITS; VLSI CIRCUITS;

ACTIVITY PATTERN; ACTIVITY SENSITIVE CLOCK TREE CONSTRUCTION; CLOCK GATING; CLOCK NETWORKS; LOW POWER DESIGN; POWER CONSUMPTION;

INTEGRATED CIRCUIT LAYOUT;

EID: 0036953969     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/566475.566481     Document Type: Conference Paper

References (6)

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