Gate planning during placement for gated clock network

26th IEEE International Conference on Computer Design 2008, ICCD

Volumn , Issue , 2008, Pages 128-133

  Weixiang, Shen ^a   Yici, Cai ^a   Xianlong, Hong ^a   Jiang, Hu ^b  

^a TSINGHUA UNIVERSITY   (China)

^b Department of Electrical and Computer Engineering   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CLOCKS; MARINE BIOLOGY;

BENCHMARK CIRCUITS; CELL OVERLAPS; CELL PLACEMENTS; CLOCK BUFFERS; CLOCK NETWORKS; CLOCK TREES; CLOCK-GATING; CONTROL GATES; GATED CLOCKS; PERFORMANCE IMPROVEMENTS; PLACEMENT LEGALIZATIONS; PLANNING TECHNIQUES; POST-PROCESSING; POWER ESTIMATIONS; POWER REDUCTIONS; REDUCING POWER; RESEARCH EFFORTS; TREE CONSTRUCTIONS; WIRE LENGTHS;

TELECOMMUNICATION NETWORKS;

EID: 62349084032     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2008.4751851     Document Type: Conference Paper

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