Power reduction in microprocessor chips by gated clock routing

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 1998, Pages 313-318

  Oh, Jaewon ^a   Pedram, Massoud ^a  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL INTEGRATED CIRCUITS; DYNAMIC PROGRAMMING; ELECTRIC NETWORK TOPOLOGY; HEURISTIC METHODS; TIMING CIRCUITS; TREES (MATHEMATICS); VLSI CIRCUITS;

CLOCK TREE TOPOLOGY; GATE CONTROL SIGNALS; GATED CLOCK ROUTING;

MICROPROCESSOR CHIPS;

EID: 0032218661     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (8)