Activity-aware registers placement for low power gated clock tree construction

Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures

Volumn , Issue , 2007, Pages 383-388

  Weixiang, Shen ^a   Yici, Cai ^a   Xianlong, Hong ^a   Jiang, Hu ^b  

^a TSINGHUA UNIVERSITY   (China)

^b Department of Electrical and Computer Engineering   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CLOCKS; ELECTRIC POWER UTILIZATION; NETWORK ROUTING; OPTIMIZATION; TREES (MATHEMATICS);

CLOCK GATING; CLOCK ROUTING; CLOCK TREE; HIGH PERFORMANCE VLSI DESIGNS;

VLSI CIRCUITS;

EID: 36349018183     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2007.20     Document Type: Conference Paper

References (13)

1. Nir Magen, Avinoam Kolodny, Uri Weiser, Nachum Shamir, "Interconnect-dissipation in a Microprocessor", in Proc. SLIP, pp. 7-13, 2004.
2. Chunhong Chen, Changjun Kang, Majid Sarrafzadeh, "Activity-sensitive clock tree construction for low power", in Proc. ISLPED, pp. 279-282, 2002.
3. A. Farrahi, C. Chen, A. Srivastava, G. Tellez, M. Sarrafzadeh, "Activity-driven clock design", IEEE Transactions on CAD/ICAS, Vol. 20, No. 6, pp. 705-714, June 2001.
4. Jaewon Oh and Massoud Pedram, "Power reduction in microprocessor chips by gated clock routing", in Proc. ASPDAC, pp. 313-318, 1998.
5. Jaewon Oh and Massoud Pedram, "Gated clock routing for low-power microprocessor design", IEEE Transactions on CAD/ICAS, Vol. 20, No. 6, pp. 715-722, June, 2001.
6. Monica Donno, Alessandro Ivadldi, Luca Benini, Enrico Macii, "Clock-tree power optimization based on RTL clock-gating", in Proc. DAC, pp. 622-627, 2003.
7. Monica Donno, Enrico Macii, Luca Mazzoni, "Power-aware clock tree planning", in Proc. ISPD, pp. 138-147, 2004.
8. Jatuchai Pangjun and Sachin S. Sapatekar, "Low-power clock distribution using multiple voltages and reduced swings", IEEE Transactions on CAD/ICAS, Vol. 10, No. 3, pp. 715-722, June, 2002.
9. Yongqian Lu, C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, et al, "Navigating registers in placement for clock network minimization", in Proc. DAC, pp. 176-181, 2005.
10. Yongseok Cheon, Pei-Hsin Ho, et al, "Power-Aware Placement", in Proc. DAC, pp. 795-800, 2005.
11. http://vlsicad.eecs.umich.edu/BK/PDtools/.
12. T. Kong, "A novel net weighting algorithm for timing-driven placement", in Proc. ICCAD, pp. 172-176, 2002.
13. Bin Liu, Yici Cai, Qiang Zhou, Xianlong Hong, "Power driven placement with layout aware supply voltage assignment for voltage island generation in dual-Vdd design", in Proc. ASP-DAC, pp. 582-587, 2006.