Power minimization by clock root gating

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2003-January, Issue , 2003, Pages 249-254

  Wang, Qi ^a   Roy, S ^a  

^a CADENCE DESIGN SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK DISTRIBUTION NETWORKS; COMPUTER AIDED DESIGN; FORESTRY; GRAPHIC METHODS; MICROPROCESSOR CHIPS; OPTIMIZATION; RECONFIGURABLE HARDWARE; TREES (MATHEMATICS);

CLOCK GATING; CLOCK TREE SYNTHESIS; GRAPH-BASED ALGORITHMS; INDUSTRIAL CIRCUITS; OPTIMIZATION PROBLEMS; POWER MINIMIZATION; POWER SAVINGS; REAL POWER;

CLOCKS;

EID: 84954437361     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2003.1195024     Document Type: Conference Paper

References (7)

1. L. Benini and G. De Micheli, "Automatic synthesis of low power gated clock finite state machine," IEEE Trans. Computer-Aided Design, vol. 15, pp. 630-643, June 1996
2. A. Farrahi, C. Chen, A. Srivastava, G. Tellez, and M. Sarrafzadeh, "Activity driven clock design," IEEE Trans. Computer-Aided Design, vol. 20, pp. 705-714, June 2001.
3. J. Oh and M. Pedram, "Gated clock routing for low power microprocessor design,", IEEE Trans. Computer-Aided Design, vol. 20, pp. 715-722, June 2001.
4. D. Garrett, M. Stan and A. Dean. "Challenges in Clock-gating for a Low Power ASIC Methodology," International Symposium on Low Power Electronic Design (ISLPED), pp. 176-181, August 1999.
5. T. Kitahara and et. al., "A Clock-Gating Method for Low Power LSI Design," International Symposium on Low Power Electronic Design (ISLPED), August 1998.
6. D. Garrett, "A Low Power Normalized-LMS Decision Feedback Equalizer for a Wireless Packet Modem", Proceeding of ISLPED, August 2002.
7. Cadence® Low Power Synthesis (LPS) User's Guide for Cadence® PKS.