Proposal and performance analysis of normally off n++ GaN/InAlN/AlN/GaN HEMTs with 1-nm-thick InAlN barrier

IEEE Transactions on Electron Devices

Volumn 57, Issue 9, 2010, Pages 2144-2154

  Kuzmik, Jan ^a,b   Ostermaier, Clemens ^b   Pozzovivo, G ^c   Basnar, Bernhard ^b   Schrenk, Werner ^b   Carlin, Jean Franois ^d   Gonschorek, M ^d   Feltin, Eric ^d   Grandjean, Nicolas ^d   Douvry, Y ^e   Gaquiere, Christophe ^e   De Jaeger, Jean Claude ^e   Cico K ^b   Fröhlich, Karol ^b   Skriniarova J ^f   Kováč, Jaroslav ^f   Strasser, Gottfried ^b   Pogany, Dionyz ^b   Gornik, Erich ^b  

^a VIENNA UNIVERSITY OF TECHNOLOGY   (Austria)

^b INSTITUTE OF ELECTRICAL ENGINEERING   (Slovakia)

^c INFINEON TECHNOLOGIES AUSTRIA AG   (Austria)

^d EPFL   (Switzerland)

^e Institut d'Electronique   (France)

^f SLOVAK UNIVERSITY OF TECHNOLOGY   (Slovakia)

Author keywords

Current collapse; gate recess; high electron mobility transistors (HEMTs); InAlN GaN; normally off; OFF state breakdown

Indexed keywords

CURRENT COLLAPSE; GATE RECESS; INALN/GAN; NORMALLY OFF; OFF-STATE BREAKDOWN;

CUTOFF FREQUENCY; DOPING (ADDITIVES); DRAIN CURRENT; ELECTRIC CURRENT MEASUREMENT; ELECTRON MOBILITY; FIELD EFFECT TRANSISTORS; GALLIUM ALLOYS; GALLIUM NITRIDE; PLASMA ETCHING; THRESHOLD VOLTAGE;

HIGH ELECTRON MOBILITY TRANSISTORS;

EID: 77956058415     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2010.2055292     Document Type: Article

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