A low-overhead and reliable switch architecture for Network-on-Chips

Integration, the VLSI Journal

Volumn 43, Issue 3, 2010, Pages 268-278

  Patooghy, Ahmad ^a   Ghassem Miremadi, Seyed ^a   Fazeli, Mahdi ^a  

^a SHARIF UNIVERSITY OF TECHNOLOGY   (Iran)

Author keywords

Flow control; Modeling; Networks on Chip; Reliability; Virtual Channel

Indexed keywords

ANALYTICAL PERFORMANCE; BIT-FLIPS; HARDWARE REDUNDANCY; INFORMATION REDUNDANCIES; MODELING; NETWORK-ON-CHIPS; NETWORKS-ON-CHIP; RELIABILITY ENHANCEMENT; RELIABILITY MODEL; RETRANSMISSIONS; SIMULATION RESULT; SWITCH ARCHITECTURES; VIRTUAL CHANNELS; WORKING CONDITIONS;

COMPUTER SIMULATION; MICROPROCESSOR CHIPS; NETWORK ARCHITECTURE; QUALITY ASSURANCE; REDUNDANCY; ROUTERS;

SWITCHING CIRCUITS;

EID: 77955712711     PISSN: 01679260     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.vlsi.2010.02.003     Document Type: Article

References (49)

1. S. Kumar, A. Jantsch, J.P. Soininen, M. Forsell, M. Millberg, J. Oberg, K. Tiensyrja, and A. Hemani A network on chip architecture and design methodology Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2002 117 122
2. L. Benini, and G. De Micheli Networks on Chips: A new SoC paradigm IEEE Computers 35 1 2002 70 78
3. A. Andrei, M. Schmitz, P. Eles, Z. Peng, B. Al-Hashimi, Simultaneous communication and processor voltage scaling for dynamic and leakage energy reduction in time-constrained systems, in: Proceedings of the International Conference on Computer Aided Design (ICCAD), 2004, pp. 362369.
4. A. Ejlali, B.M. Al-Hashimi, P. Rosinger, S.G. Miremadi, Joint consideration of fault-tolerance, energy-efficiency and performance in on-chip networks, in: Proceedings of the Design, Automation, and Test in Europe (DATE), 2007, pp.16.
5. L. Shang, L.S. Peh, and N.K. Jha Dynamic voltage scaling with links for power optimization of interconnection networks Proceedings of International Symposium on High-Performance Computer Architecture (HPCA) 2003 91 102
6. M. Fazeli, A. Patooghy, S.G. Miremadi, A. Ejlali, Feedback redundancy: a power efficient SEU-tolerant latch design for deep sub-micron technologies, in: Proceedings of the International Conference on Dependable Systems and Networks (DSN), 2007, pp. 276285.
7. A. Ejlali, B.M. Al-Hashimi, M.T. Schmitz, P. Rosinger, and S.G. Miremadi Combined time and information redundancy for SEU-tolerance in energy-efficient real-time systems IEEE Transaction on Very Large Scale Integration Systems 14 2006 323 335
8. P. Hazucha, and C. Svensson Impact of CMOS technology scaling on the atmospheric neutron soft error rate IEEE Transaction Nuclear Science 47 2000 2586 2594
9. M.T. Schmitz, B.M. Al-Hashimi, and P. Eles System-Level Design Techniques for Energy-Efficient Embedded Systems 2004 Kluwer Academic Publisher
10. T.D. Burd, T.A. Pering, A.J. Stratakos, and R.W. Brodersen A dynamic voltage scaled microprocessor system IEEE Journal of Solid-State Circuits 35 2000 1571 1580
11. M. Takai, T. Kishimoto, Y. Ohno, H. Sayama, K. Sonoda, S. Satoh, T. Nishimura, H. Miyoshi, A. Kinomura, Y. Horino, and K. Fujii Soft error susceptibility and immune structures in dynamic random access memories (DRAMs) investigated by nuclear microprobes IEEE Transaction Nuclear Science 43 1996 696 704
12. D.R. Blum, M.J. Myjak, J.G. Delgado-Frias, Enhanced fault-tolerant data latches for deep submicron CMOS, in: Proceedings of the International Conference of Computer Design (ICCD), 2005, pp. 2834.
13. Q. Zhou, and K. Mohanram Gate sizing to radiation harden combinational logic IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems 25 2006 155 166
14. S. Mitra, N. Seifert, M. Zhang, Q. Shi, and K.S. Kim Robust system design with built-in soft-error resilience Computer 38 2005 43 52
15. M. Nicolaidis Design for soft error mitigation IEEE Transactions on Device and Materials Reliability 5 2005 405 418
16. P. Eaton, J. Benedetto, D. Mavis, K. Avery, M. Sibley, M. Gadlage, and T. Turflinger Single event transient pulsewidth measurements using a variable temporal latch technique IEEE Transaction on Nuclear Science 51 2004 3365 3368
17. S. Krishnamohan and N.R. Mahapatra, A highly-efficient technique for reducing soft errors in static CMOS circuits, in: Proceedings of the International Conference of Computer Design (ICCD), 2004, pp. 126131.
18. Y. Hu, H. Chen, Y. Zhu, A.A. Chien, C.K. Cheng, Physical synthesis of energy-efficient networks-on-chip through topology exploration and wire style optimization, in: Proceedings of the International Conference of Computer Design (ICCD), 2005, pp. 111118.
19. T. Dumitras, S. Kerner, R. Marculescu, Towards on-chip fault-tolerant communication, in: Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), 2003, pp. 225232.
20. R. Karp, C. Schindelhauer, S. Shenker, and B. Vocking Randomized rumor spreading Proceedings of the Annual IEEE Symposium on Foundations of Computer Science (FOCS) 2000 656
21. M. Pirretti, G.M. Link, R.R. Brooks, N. Vijaykrishnan, M. Kandemir, and M.J. Irwin Fault-tolerant algorithms for Network-on-Chip interconnect Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2004 46 51
22. J. Wu A fault-tolerant and deadlock-free routing protocol in 2D meshes based on odd-even turn model IEEE Transaction on Computer 52 2003 1154 1169
23. T. Valtonen, T. Nurmi, J. Isoaho, and H. Tenhunen Interconnection of autonomous error tolerant cells Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) 2002 473 476
24. M.A. Schuette, and J.P. Shen Processor control flow monitoring using signatured instruction streams, IEEE Transactions on Computers C-36 1987 264 277
25. S. Murali, T. Theocharides, N. Vijaykrishnan, M.J. Irwin, L. Benini, and G. De Micheli Analysis of error recovery schemes for Networks-on-Chips IEEE Design and Test of Computers 22 5 2005 434 442
26. D. Bertozzi, L. Benini, G. De Micheli, Low power error-resilient encoding for on-chip data buses, in: Proceedings of the Design, Automation, and Test in Europe (DATE), March 2002, pp. 102109.
27. P. Vellanki, N. Banerjee, and K.S. Chatha Quality-of-service and error control techniques for Network on Chip architectures Proceedings of GLSVLSI 2004 45 50
28. H. Zimmer, A. Jantsch,A fault model notation and error-control scheme for switch-to-switch buses in a Network-on-Chip, in: Proceedings of the International Conference on Hardware-Software Codesign and System Synthesis (ISSS/CODES), 2003, pp. 188193.
29. W.J. Dally, B. Towles, Route packets, not wires: on-chip interconnection networks, in: Proceedings of Design Automation Conference (DAC), 2001, pp 684689.
30. D. Park, C. Nicopoulos, J. Kim, N. Vijaykrishnan, C.R. Das, Exploring fault-tolerant Network-on-Chip architectures, in: Proceedings of the International Conference on Dependable Systems and Networks (DSN), 2006, pp. 93104.
31. S. Kumar, A. Jantsch, J.P. Soininen, M. Forsell, M. Millberg, J. Oberg, K. Tiensyrja, and A. Hemani A network on chip architecture and design methodology IEEE Computer Society Annual Symposium on VLSI 2002 105 112
32. J. Duato, S. Yalamanchili, and L. Ni Interconnection Networks: An Engineering Approach 2002 Morgan Kaufman Publication
33. W.J. Dally, and J.W. Poulton Digital Systems Engineering 1998 Cambridge University Press
34. N. Seifert, D. Moyer, N. Leland, and R. Hokinson Historical trend in alpha-particle induced soft error rates of the alpha microprocessor Proceedings of Reliability Physics Symposium (RPS) 2001 259 265
35. A. Maheshwari, W. Burleson, and R. Tessier Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits IEEE Transactions on VLSI 12 2004 299 311
36. M. Ould-Khaoua, and H. Sarbazi-Azad An analytical model of adaptive wormhole routing in hypercubes in the presence of hot spot traffic IEEE Transactions on Parallel and Distributed Systems 12 3 2001 283 292
37. A. Patooghy, and H. Sarbazi-Azad Analytical performance modeling of partially adaptive routing in wormhole hypercubes Proceedings of the International Parallel and Distributed Processing Symposium (IPDPS) 2006 153 159
38. H. Sarbazi-Azad A mathematical model of deterministic wormhole routing in hypercube multicomputers using virtual channels Applied Mathematical Modeling 27 12 2003 943 953
39. H.R. Zarandi, and S.G. Miremadi Dependability evaluation of Altera FPGA-based embedded systems subjected to SEUs Microelectronics Reliability 47 2007 461 470
40. M. Fazeli, and S.G. Miremadi A power efficient masking technique for design of robust embedded systems against SEUs and SETs Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT) 2008 193 201
41. M. Nicolaidis Design for soft error mitigation IEEE Transactions on Device and Materials Reliability 5 2005 405 418
42. A. Patooghy, M. Fazeli, and S.G. Miremadi A low-power and SEU-tolerant switch architecture for Network on Chips Proceedings of the Pacific Rim International Symposium on Dependable Computing (PRDC) 2007 264 267
43. A. Patooghy, S.G. Miremadi, Reliability & performance modeling to speed-up the NoC design, in: Proceedings of the 15th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2009), 2009, pp. 208213.
44. K. Constantinides, S. Plaza, J. Blome, Z. Bin, V. Bertacco, S. Mahlke, T. Austin, and M. Orshansky BulletProof: a defect-tolerant CMP switch architecture Proceedings of High-Performance Computer Architecture (HPCA) 2006 3 14
45. D. Bertozzi, L. Benini, G. De Micheli, Low power error resilient encoding for on-chip data buses, in: Proceedings of Design, Automation and Test in Europe Conference (DATE), 2002, pp. 102109.
46. A.P. Frantz, L. Carro, F. Cota, and F.L. Kastensmidt Evaluating SEU and crosstalk effects in Network-on-Chip routers Proceedings of the IEEE International On-Line Testing Symposium (IOLTS) 2002 191 192 (Pubitemid 46603896)
47. S. Manolache, P. Eles, Z. Peng, Fault and energy-aware communication mapping with guaranteed latency for applications implemented on NoC, in: Proceedings of the 42nd Annual Conference on Design automation DAC, 2005, San Diego, CA, USA.
48. J. Kim, Do. Park, C. Nicopoulos, N. Vijaykrishnan, and C.R. Das Design and analysis of an NoC architecture from performance, reliability and energy perspective Proceedings of the ACM Symposium on Architecture for networking and communications systems 2005 173 182
49. S. Murali, D. Atienza, L. Benini, G. De Micheli, A multipath routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chip, in: Proceedings of the 43rd ACM/IEEE Design Automation Conference (DAC), 2006, pp. 845848.