Quality-of-service and error control techniques for network-on-chip architectures

Proceedings of the ACM Great Lakes Symposium on VLSI

Volumn , Issue , 2004, Pages 45-50

  Vellanki, Praveen ^a   Banerjee, Nilanjan ^a   Chatha, Karam S ^a  

^a ARIZONA STATE UNIVERSITY   (United States)

Author keywords

Error detection correction; Interconnection networks; Networks on Chip; Performance; Power; Quality of Service

Indexed keywords

ERROR DETECTION; INTERCONNECTION NETWORKS; JITTER; MULTIMEDIA SYSTEMS; QUALITY OF SERVICE; ROUTERS; SPURIOUS SIGNAL NOISE; SWITCHING; TELECOMMUNICATION TRAFFIC;

NETWORKS-ON-A-CHIP (NOC); NOC ROUTERS; POWER ERROR CONTROL SCHEMES; SIGNAL TRANSMISSION;

MICROPROCESSOR CHIPS;

EID: 2942641861     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/988952.988964     Document Type: Conference Paper

References (16)

1. D. Sylvester and K. Keutzer. "A Global Wiring Paradigm for Deep Submicron Design". IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, pages 242-252, February 2000.
2. R.Ho, K. Mai and M. Horowitz. "The Future of Wires". Proceedings of IEEE, pages 490-504, April 2001.
3. J.A. Davis and J.D. Meindl. "Compact Distributed RLC Interconnect Models - Part II: Coupled Line Transient Expressions and Peak Crosstalk in Multilevel Networks". IEEE Transactions on Electron Devices, 47(11);2078-2087, November 2000.
4. William J. Dally and Brian Towles. "Route Packet, Not Wires: On-Chip Interconnection Networks". In Proceedings of DAC, June 2001.
5. Luca Benini and Giovanni De Micheli. "Networks on Chips: A New SoC Paradigm". IEEE Computer, pages 70-78, January 2002.
6. S. Lin and D. J. Costello. "Error Control Coding: Fundamentals and Applications". Prentice-Hall Inc., 1983.
7. N. Banerjee, P. Vellanki and K. S. Chatha. "A Power and Performance Model for Network-on-Chip Architectures". In DATE, 2004.
8. A.G. Wassal and M.A. Hasan. "Low-power system-level design of VLSI packet switching fabrics". IEEE Transactions on CAD, 20:723-738, June 2001.
9. Terry T. Ye, Luca Benini and Giovanni De Micheli. "Analysis of Power Consumption on Switch Fabrics in Network Routers". In Proceedings of DAC, 2002.
10. H-S Wang, L-S Peh and S. Malik. "Orion: A Power-Performance Simulator for Interconnection Network". In International Symposium on Microarchitecture, Istanbul, Turkey, November 2002.
11. E. Rijpkema, K. G. W. Goossens, and A. Radulescu. "Trade Offs in the Design of a Router with Both Guaranteed Best-Effort Services for Networks on chip". In DATE, 2003.
12. D. Bertozzi, L. Benini, and G. De Micheli. "Low power error resilient encoding for on-chip data buses". In DATE, 2003.
13. H. Zimmer and A. Jantsch. "A Fault Model Notation and Error-Control Scheme for switch-to-Switch Buses in a Network-on-Chip". In ISSS/CODES, 2003.
14. Berkeley Predictive Technology Modeling. "http://www-device.eecs. berkely.edu/-ptm". Technical report.
15. R. Hegde and N. Shanbhag. "Towards Achieving Energy Efficiency in Presence of Deep Submicron Noise". IEEE Transactions on VLSI, 8(4):379-391, August 2000.
16. L. Li, N. Vijaykrishnan, M. Kandemir, M. J. Irwin. "Adaptive Error Protection For Energy Efficieny". In ICCAD, 2003.