Cache vulnerability equations for protecting data in embedded processor caches from soft errors

Proceedings of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)

Volumn , Issue , 2010, Pages 143-152

  Shrivastava, Aviral ^a   Lee, Jongeun ^b   Jeyapaul, Reiley ^a  

^a ARIZONA STATE UNIVERSITY   (United States)

^b Ulsan National Institute of Science and Technology   (South Korea)

Author keywords

cache vulnerability; code transformation; compiler technique; embedded processors; soft errors; static analysis

Indexed keywords

CACHE VULNERABILITY; CODE TRANSFORMATION; COMPILER TECHNIQUES; EMBEDDED PROCESSORS; SOFT ERROR; SOFT ERRORS;

COMMERCE; COSINE TRANSFORMS; COSMOLOGY; DESIGN; EMBEDDED SYSTEMS; ERROR CORRECTION; LINGUISTICS; MICROPROCESSOR CHIPS; MOBILE TELECOMMUNICATION SYSTEMS; NANOTECHNOLOGY; STATIC ANALYSIS;

PROGRAM COMPILERS;

EID: 77954463983     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1755888.1755910     Document Type: Conference Paper

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