Aggressive leakage reduction of SRAMs using error checking and correcting (ECC) techniques

Midwest Symposium on Circuits and Systems

Volumn , Issue , 2008, Pages 426-429

  Nourivand, Afshin ^a   Al Khalili, Asim J ^a   Savaria, Yvon ^b  

^a Dept of Electrical and Computer Engineering   (Canada)

^b ÉCOLE POLYTECHNIQUE DE MONTRÉAL   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

BIAS VOLTAGE; NETWORKS (CIRCUITS); PROBABILITY DISTRIBUTIONS; RANDOM ACCESS STORAGE; STATIC RANDOM ACCESS STORAGE;

CRITICAL VOLTAGES; ECC SCHEMES; ERROR-CHECKING; HAMMING CODES; LEAKAGE REDUCTION TECHNIQUES; LEAKAGE REDUCTIONS; POWER REDUCTIONS; PROBABILISTIC MODELS; PROCESS VARIATIONS; RANDOM ACCESSES; RELIABLE; SRAM ARRAYS; STANDBY MODES;

LEAKAGE CURRENTS;

EID: 54249122248     PISSN: 15483746     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MWSCAS.2008.4616827     Document Type: Conference Paper

References (6)

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