Harmony: static noise analysis of deep submicron digital integrated circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 18, Issue 8, 1999, Pages 1132-1150

  Shepard, Kenneth L ^a   Narayanan, Vinod ^b   Rose, Ron ^c  

^a Department of Biomedical Engineering   (United States)

^b CadMOS Design Technology   (United States)

^c IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; CONSTRAINT THEORY; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; SPURIOUS SIGNAL NOISE; VLSI CIRCUITS;

DEEP SUBMICRON INTEGRATED CIRCUITS; INTERCONNECT COUPLING; INTERCONNECT MODELS; STATIC NOISE ANALYSIS; STATIC TIMING ANALYSIS; TRANSISTOR LEVEL ANALYSIS;

DIGITAL INTEGRATED CIRCUITS;

EID: 0032681122     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.775633     Document Type: Article

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