Static analysis to mitigate soft errors in register files

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2009, Pages 1367-1372

  Lee, Jongeun ^a   Shrivastava, Aviral ^a  

^a AZ 85281   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPILER OPTIMIZATIONS; COST-EFFECTIVE PROTECTION; INHERENT COMPLEXITY; REGISTER FILES; RUNTIME OVERHEADS; SOFT ERROR; STATIC ESTIMATION; TECHNOLOGY SCALING;

ERROR CORRECTION; ESTIMATION; MICROPROCESSOR CHIPS; STATIC ANALYSIS;

PROGRAM COMPILERS;

EID: 70350070719     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (25)

1. "International technology roadmap for semiconductors 2007 executive summary." [Online]. Available: http://www.itrs.net/.
2. J. A. Blome et al., "Cost-efficient soft error protection for embedded microprocessors," in CASES '06, 2006, pp. 421-431.
3. S. Mitra et al., "Robust system design with built-in soft-error resilience," IEEE Computer, vol. 38, pp. 43-52, 2005.
4. A. Shrivastava et al., "Operation tables for scheduling in the presence of incomplete bypassing." in CODES+ISSS, 2004, pp. 194-199.
5. K. Skadron et al., "Temperature-aware microarchitecture, " in Proc. Int'l Symp. on Computer Architecture, 2003, pp. 2-13.
6. P. Dodd and L. Massengill, "Basic mechanisms and modeling of single-event upset in digital microelectronics," IEEE Trans. on Nuclear Science, vol. 50, pp. 583-602, June 2003.
7. P. Dodd et al., "Neutron-induced latchup in SRAMs at ground level," in 41st Annual Int'l Reliability Physics Symposium, 2003, pp. 51-55.
8. J. Hasan et al., "Heat stroke: Power-density-based denial of service in SMT," in HPCA, 2005.
9. S. Park et al., "Bypass aware instruction scheduling for register file power reduction," in LCTES, 2006, pp. 173-181.
10. G. Memik et al., "Engineering over-clocking: reliability-performance trade-offs for high-performance register files," DSN '05, 2005.
11. P. Montesinos et al., "Using register lifetime predictions to protect register files against soft errors," in DSN '07, 2007, pp. 286-296.
12. M. Kandala et al., "An area-efficient approach to improving register file reliability against transient errors," in ISEC, 2007.
13. Compiler-Managed Register File Protection for Energy-Efficient Soft Error Reduction, 2009.
14. J. Yan and W. Zhang, "Compiler-guided register reliability improvement against soft errors," in EMSOFT '05, 2005, pp. 203-209.
15. S. S. Mukherjee et al., "A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor," in Proc. International Symposium on Microarchitecture, Dec 2003.
16. T. J. Slegel et al., "IBM's S/390 G5 microprocessor design," IEEE Micro, vol. 19, pp. 12-23, 1999.
17. X. Li et al., "Online estimation of architectural vulnerability factor for soft errors," SIGARCH Comput. Archit. News, vol. 36, pp. 341-352, 2008.
18. K. R. Walcott et al., "Dynamic prediction of architectural vulnerability from microarchitectural state," SIGARCH CA News, pp. 516-527, 2007.
19. K. Chen et al., "Retargetable static timing analysis for embedded software," in ISSS '01, 2001, pp. 39-44.
20. S. Chatterjee et al., "Exact analysis of the cache behavior of nested loops," in PLDI '01, 2001, pp. 286-297.
21. D. Patterson and J. Hennessy, Computer Organization and Design: The Hardware/Software Interface. Morgan Kaufmann Publishers, 2004.
22. M. Guthaus et al., "Mibench: A free, commercially representative embedded benchmark suite," in IWWC, 2001.
23. T. Austin, "SimpleScalar LLC."
24. Y. Wu and J. Larus, "Static branch frequency and program profile analysis," in MICRO 27, 1994, pp. 1-11.
25. "Open-source mixed-integer linear programming system." [Online]. Available: http://lpsolve.sourceforge.net/5.5/