Complement routing: A methodology to design reliable routing algorithm for Network on Chips

Microprocessors and Microsystems

Volumn 34, Issue 6, 2010, Pages 163-173

  Patooghy, Ahmad ^a   Miremadi, Seyed Ghassem ^a  

^a SHARIF UNIVERSITY OF TECHNOLOGY   (Iran)

Author keywords

Fault injection; Network on chip; Reliability; Routing algorithm

Indexed keywords

ANALYTICAL APPROACH; DEEP SUB-MICRON; DEPENDENCY GRAPHS; DISJOINT SETS; ERROR INJECTION; FAULT INJECTION; FIRST ORDER; MINIMAL POWER; NETWORK ON CHIP; POWER CONSUMPTION; RELIABILITY IMPROVEMENT; RELIABLE ROUTING ALGORITHMS; SYNOPSYS; TRAFFIC GENERATION; VLSI TECHNOLOGY;

DISTRIBUTED COMPUTER SYSTEMS; FAULT TOLERANT COMPUTER SYSTEMS; MICROPROCESSOR CHIPS; RELIABILITY;

ROUTING ALGORITHMS;

EID: 77954198569     PISSN: 01419331     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.micpro.2010.03.002     Document Type: Article

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