Using Implications for Online Error Detection

Proceedings - International Test Conference

Volumn , Issue , 2008, Pages

  Nepal, K ^a   Alves, N ^b   Dworak, J ^b   Bahar, R I ^b  

^a BUCKNELL UNIVERSITY   (United States)

^b Brown University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AREA OVERHEAD; CRITICAL PATHS; HARDWARE OVERHEADS; INTERMITTENT FAULT; MANUFACTURING DEFECTS; ON-LINE DETECTION; ON-LINE ERROR DETECTION;

ELECTRIC FAULT CURRENTS;

ERROR DETECTION;

EID: 67249133913     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TEST.2008.4700614     Document Type: Conference Paper

References (39)

1. Yael Abarbanel, Ilan Beer, Leonid Glushovsky, Sharon Keidar, and Yaron Wolfsthal. FoCs: automatic generation of simulation checkers from formal specifications. In CAV '00: Proceedings of the 12th International Conference on Computer Aided Verification, pages 538-542, 2000.
2. S. Almukhaizim, P. Drineas, and Y. Makris. Costdriven selection of parity trees. In VLSI Test Symposium, pages 319-324, 25-29 April 2004.
3. Sobeeh Almukhaizim, Yiorgos Makris, Yu-Shen Yang, and Andreas Veneris. Seamless integration of SER and rewiring-based design space exploration. In International Test Conference, pages 1-9, Oct. 2006.
4. T. M. Austin. Diva: A reliable substrate for deepsubmicron microarchitecture design. In Proceedings of the 32nd Annual International Symposium on Microarchitecture, pages 196-207, November 1999.
5. R.I. Bahar, M. Burns, G. Hachtel, E. Macii, H. Shin, and F. Somenzi. Symbolic computation of logic implications for technology-dependent low-power synthesis. In Proceedings of the International Symposium On Low Power Electronics And Design, pages 163-168, Monterey, CA, USA, August 1996.
6. J. M. Berger. A note on an error detection code for asymmetric channels. Information and Control, 4:68-73, 1961.
7. Dilip K. Bhavsar. An algorithm for row-column selfrepair of RAMS and its implementation in the Alpha 21264. In Proceedings of th 1999 International Test Conference, pages 311-318, 1999.
8. S. Bobba and I.N. Hajj. Estimation of maximum current envelope for power bus analysis and design. In Proceedings of the International Symposium on Physical Design, pages 141-146, Monterey, CA, USA, April 1998.
9. B. Bose and D. J. Lin. Systematic unidirectional errordetecting codes. IEEE Transactions on Computers, C-34:1026-1032, 1985.
10. Marc Boule, Jean-Samuel Chenard, and Zeljko Zilic. Assertion checkers in verification, silicon debug and infield diagnosis. In ISQED '07: Proceedings of the 8thInternational Symposium on Quality Electronic Design, pages 613-620, 2007.
11. F.M. Brown. Boolean Reasoning. Kluwer Academic Publishers, Hingham, MA, USA, 1990.
12. M. Choi, N. Park, F. Lombardi, Y.B. Kim, and V. Piuri. Balanced redundancy utilization in embeddedmemory cores for dependable systems. In Proceedings 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pages 419-427, December 2002.
13. D. Das and N. A. Touba. Synthesis of circuits withlow-cost concurrent error detection based on Bose-Lin codes. In VLSI Test Symposium, pages 309-315, 1998.
14. K. De, C. Natarajan, D. Nair, and P. Banerjee. RSYN: a system for automated synthesis of reliable multilevelcircuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2:786-1195, 1994.
15. Rolf Drechsler. Synthesizing checkers for on-line ve Reification of system-on-chip designs. In ISCAS '03: Proceedings of the 2003 International Symposium on Circuitsand Systems, pages IV-748 - IV-751, May 25-28 2003.
16. P. Drineas and Y. Makris. Concurrent fault detection in random combinational logic. In Proceedings Fourth International Symposium on Quality Electronic Design ISQED, pages 425-430, March 2003.
17. S. Ghosh, N.A. Touba, and S. Basu. Synthesis of low power ced circuits based on parity codes. In VLSI Test Symposium, pages 315-320, 1-5 May 2005.
18. A. Glebov, S. Gavrilov, D. Blaauw, and V. Zolotov. False-noise analysis using logic implications. ACM Trans. Des. Autom. Electron. Syst., 7(3):474-498, 2002.
19. M. A. Gomaa and T. N. Vijaykumar. Opportunistic transient-fault detection. In Proceedings of the 32nd Annual International Symposium on Computer Architecture, June 2005.
20. Michael Gössel, Error Detection Circuits. McGraw- Hill, London, NY, USA, 1993.
21. Smita Krishnaswamy, Stephen M. Plaza, Igor L. Markov, and John P. Hayes. Enhancing design robustness with reliability-aware resynthesis and logic simulation. In ICCAD, pages 149-154, Nov. 2007.
22. W. Kunz and P.R. Menon. Multi-level logic optimization by implication analysis. In Proceedings of the International Conference on Computer-Aided Design, pages 6-10, San Jose, CA, USA, November 1994.
23. Y. Mahajan, Z. Fu, and S. Malik. Zchaff2004: An efficient sat solver. Lecture Notes in Computer Science, 3542:360-375, 2005.
24. S. Mitra and E.J. McCluskey. Which concurrent error detection scheme to choose? In Proceedings International Test Conference, pages 985-994, October 2000.
25. K. Mohanram, E. Sogomonyan, M. Gossel, and N. Touba. Synthesis of low-cost parity-based partially self-checking circuits, 2003.
26. K. Mohanram and N.A. Touba. Cost-effective approach for reducing soft error failure rate in logic circuits. In Proceedings International Test Conference, pages 893-901, October 2003.
27. J. Ray, J. C. Hoe, and B. Falsafi. Dual use of superscalar datapath for transient-fault detection and recovery. In Proceedings of the 34th annual IEEE/ACM international symposium on Microarchitecture, pages 214-244, 2001.
28. S. K. Reinhardt and S. S. Mukherjee. Transient-fault detection via simultaneous multithreading. In Proceedings of the 27th Annual International Symposium on Computer Architecture, pages 25-36, June 2000.
29. Bernhard Rohfleisch, Alfred Kölbl, and Bernd Wurth. Reducing power dissipation after technology mapping by structural transformations. In Design Automation Conference, pages 789-794, New York, NY, USA, 1996. ACM.
30. R. Sedmak and H. Liebergot. Fault tolerance of a general purpose computer implemented by very large scale integration. IEEE Transactions on Computers, C-29:492-500, 1980.
31. R. Sedmak and H. Liebergot. Selective triple modular redundancy (STMR) based single-event upset (SEU) tolerant synthesis for FPGAs. IEEE Transactions on Nuclear Science, 51:2957-2969, 2005.
32. R. Sharma and K.K. Saluja. An implementation and analysis of a concurrent built-in self-test technique. InDigest of Papers Eighteenth International Symposium on Fault-Tolerant Computing FTCS-18, pages 164- 169, June 1988.
33. E. S. Sogomonjan and Michael Gössel. Design of self-parity combinational circuits for self- testing andon-line detection. In Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, pages 239-246, Washington, DC, USA, 1993. IEEE Computer Society.
34. K. Sundaramoorthy, Z. Purser, and E. Rotenberg. Slipstream processors: Improving both performanceand fault-tolerance. In Proceedings of the Ninth International Symposium on Architectural Support for Programming Languages and Operating Systems, pages 257-268, November 2000.
35. P. Tafertshofer, A. Ganz, and M. Henftling. A SATbased implication engine for efficient ATPG, equivalence checking, and optimization of netlists. In Proceedings of the International Conference on Computer- Aided Design, pages 648-655, San Jose, CA, USA, November 1997.
36. N.A. Touba and E.J. McCluskey. Logic synthesis of multilevel circuits with concurrent error detection. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 16(7):783-789, Jul 1997.
37. M. R. Trinka. Defect site prediction based upon statistical analysis of fault signatures. Master's thesis, Texas A&M University, August 2003.
38. J. von Neumann. Probabilistic logics and synthesis of reliable organisms from unreliable components. In C. Shannon and J. McCarthy, editors, Automata Studies, pages 43-98. Princeton University Press, 1956.
39. C. F. Webb and J. S. Liptay. A high frequency custom CMOS S/390 microprocessor. IBM Journal of Research and Development, 41:463-473, 1997.