Fully depleted extremely thin SOI technology fabricated by a novel integration scheme featuring implant-free, zero-silicon-loss, and faceted raised source/drain

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2009, Pages 212-213

  Cheng, K ^a   Khakifirooz, A ^a   Kulkarni, P ^a   Kanakasabapathy, S ^a   Schmitz, S ^a   Reznicek, A ^a   Adam, T ^a   Zhu, Y ^b   Li, J ^a   Faltermeier, J ^a   Furukawa, T ^a   Edge, L F ^a   Haran, B ^a   Seo, S C ^a   Jamison, P ^a   Holt, J ^a   Li, X ^a   Loesing, R ^a   Zhu, Z ^a   Johnson, R ^a   Upham, A ^a   Levin, T ^a   Smalley, M ^a   Herman, J ^a   Di, M ^a   Wang, J ^a   Sadana, D ^b   Kozlowski, P ^a   Bu, H ^a   Doris, B ^a   O'Neill, J ^a   more..

^a IBM RESEARCH   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DRIVE CURRENTS; FULLY DEPLETED; GATE LENGTH; INTEGRATION SCHEME; MANUFACTURING ISSUE; PARASITIC CAPACITANCE; RAISED SOURCE/DRAIN; SERIES RESISTANCES; SHORT-CHANNEL EFFECT; SMALL DEVICES; SOI CHANNELS; SUBTHRESHOLD SWING; THIN SOI;

SILICON ON INSULATOR TECHNOLOGY;

TECHNOLOGY;

EID: 71049153735     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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