SRAM cell design considerations for SOI technology

Proceedings - IEEE International SOI Conference

Volumn , Issue , 2009, Pages

  Liu, Tsu Jae King ^a   Shin, Changhwan ^a   Cho, Min Hee ^a   Sun, Xin ^a   Nikolić, Borivoje ^a   Nguyen, Bich Yen ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b SOITEC USA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BURIED OXIDES; CMOS TECHNOLOGY; COMPACT MODELING; DOPING PROFILES; FULLY DEPLETED SOI; GATE LENGTH; LINE EDGE ROUGHNESS; PROCESS-INDUCED VARIATION; SOI FINFETS; SOI TECHNOLOGY; SRAM CELL; THREE DIMENSIONAL DEVICE SIMULATIONS;

CMOS INTEGRATED CIRCUITS; SENSITIVITY ANALYSIS; STATIC RANDOM ACCESS STORAGE; THREE DIMENSIONAL;

SILICON ON INSULATOR TECHNOLOGY;

EID: 72449142757     PISSN: 1078621X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOI.2009.5318784     Document Type: Conference Paper

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