FDSOI devices with thin BOX and ground plane integration for 32 nm node and below

Solid-State Electronics

Volumn 53, Issue 7, 2009, Pages 730-734

  Fenouillet Beranger, C ^a,b   Denorme, S ^a   Perreau, P ^a,b   Buj, C ^b   Faynot, O ^b   Andrieu, F ^b   Tosti, L ^b   Barnola, S ^b   Salvetat, T ^b   Garros, X ^b   Casse M ^b   Allain, F ^b   Loubet, N ^a   Pham Nguyen, L ^a,c   Deloffre, E ^a   Gros Jean, M ^a   Beneyton, R ^a   Laviron, C ^a,b   Marin, M ^a   Leyris, C ^a   Haendler, S ^a   Leverd, F ^a   Gouraud, P ^a   Scheiblin, P ^b   Clement, L ^a   Pantel, R ^a   Deleonibus, S ^b   Skotnicki, T ^a   more..

^a STMICROELECTRONICS   (France)

^b CEA LETI   (France)

^c IMEP LAHC   (France)

Author keywords

BOX; DIBL; Fully depleted; Metal gate; Short channel effects; SOI; Subthreshold slope

Indexed keywords

BOX; DIBL; FULLY-DEPLETED; METAL GATE; SHORT-CHANNEL EFFECTS; SOI; SUBTHRESHOLD SLOPE;

NANOTECHNOLOGY;

EID: 67349140970     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2009.02.009     Document Type: Article

References (17)

1. 2 6T-SRAM bitcell. IEDM Tech Digest (2007) 267-270
2. C. Gallon et al. Ultra-thin fully depleted SOI device with thin BOX, ground plane and strained liner booster. In: IEEE international SOI conference; 2006. p. 17-8.
3. M. Fujiwara et al. Impact of BOX scaling on 30 nm gate length FD SOI MOSFETs. In: IEEE international SOI conference; 2005. p. 180-2.
4. C. Fenouillet-Beranger et al. Requirements for ultra-thin-film devices and new materials on CMOS roadmap. In: IEEE international SOI conference; 2003. p. 145-6.
5. Josse E., et al. A cost-effective low power platform for the 45 nm technology node. IEDM Tech Digest (2006) 693-696
6. z high-k dielectric. In: Proceedings of ESSDERC; 2007, p. 255-8.
7. 2 6T-SRAM Bit Cell using 45 nm fully-depleted SOI CMOS technology with metal gate, high-k dielectric and elevated source/drain on 300 mm wafers. In: IEEE international SOI conference; 2005. p. 221-2.
8. B. Doris et al. High performance FDSOI CMOS technology with metal gate and high-k. In: Symposium on VLSI technology; 2005. p. 214-5.
9. Crupi F., et al. Impact of the interfacial layer on the low frequency noise (1/f) behavior of MOSFETs with advanced gate stacks. IEEE EDL 27 8 (2006) 688-691
10. Giusi G., et al. Comparative study of drain and gate low-frequency noise in nMOSFETs with hafnium based gate dielectrics. IEEE TED 53 4 (2006) 823-827
11. x gate stacks. IEEE TED August (2004) 315-322
12. Srinivasan P., et al. Low-frequency (1/f) noise performance of n- and p-MOSFETs with poly-Si/Hf-based gate dielectrics. J ECS 153 4 (2006) 324-329
13. B. Min et al. Flicker noise in nitrided high-κ dielectric NMOS transistors. In: Proceedings of FaN, noise in devices and circuits, vol. 5844; 2005. p. 31-9.
14. K. Sukegawa et al. Dependable integration of full-porous low-k interconnect and low-leakage/low cost transistor for 45 nm LSTP platform. In: Symposium on VLSI; 2007. p. 174-75.
15. G. Tsutsui et al. A cost effective LOP/LSTP integrated CMOS platform utilizing multi-thickness SiON gate dielectrics with hafnium for 45 nm node. In: Symposium on VLSI; 2007. p. 176-77.
16. .
17. Cathignol A., et al. Improved methodology for better accuracy on transistors matching characterization. IEEE ICMTS (2006) 173-178