Systematic microwave network analysis for multilayer printed circuit boards with vias and decoupling capacitors

IEEE Transactions on Electromagnetic Compatibility

Volumn 52, Issue 2, 2010, Pages 401-409

  Zhang, Yao Jiang ^a   Oo, Zaw Zaw ^a   Wei, Xing Chang ^a   Liu, En Xiao ^a   Fan, Jun ^b   Li, Er Ping ^a  

^a INSTITUTE OF HIGH PERFORMANCE COMPUTING   (Singapore)

^b University of Missouri Rolla   (United States)

Author keywords

Decoupling capacitors; Intrinsic via circuit model; Microwave network method; Printed circuit board (PCB); Signal integrity power integrity (SI PI)

Indexed keywords

ADMITTANCE MATRICES; BOTTOM PLATE; CIRCUIT MODELS; CPU TIME; DECOUPLING CAPACITOR; HIGHER EFFICIENCY; IMPEDANCE MATRICES; MEMORY REQUIREMENTS; MICROWAVE NETWORK METHOD; MICROWAVE NETWORKS; MULTILAYER PRINTED CIRCUIT BOARD; MULTIPLE VIAS; NUMERICAL SIMULATION; NUMERICAL SOLVERS; PARALLEL PLATES; POWER INTEGRITY; RECURSIVE ALGORITHMS; SINGLE PLATES; TWO LAYERS; TWO PLATES; VIA HOLE;

CAPACITANCE; CAPACITORS; COMPUTER SIMULATION; ELECTRIC NETWORK ANALYSIS; FUZZY CONTROL; MICROWAVES; MULTILAYERS; PLATES (STRUCTURAL COMPONENTS); PRINTED CIRCUIT MANUFACTURE; QUALITY ASSURANCE;

PRINTED CIRCUIT BOARDS;

EID: 77952744877     PISSN: 00189375     EISSN: None     Source Type: Journal    
DOI: 10.1109/TEMC.2010.2040389     Document Type: Article

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