Quantifying SMT decoupling capacitor placement in dc power-bus design for multilayer PCBs

IEEE Transactions on Electromagnetic Compatibility

Volumn 43, Issue 4, 2001, Pages 588-599

  Fan, Jun ^a,b,c   Drewniak, James L ^a,b   Knighten, James L ^a,c   Smith, Norman W ^c   Orlandi, Antonio ^a,d   Van Doren, Thomas P ^a,c   Hubing, Todd H ^a,b   DuBroff, Richard E ^a,b  

^a IEEE   (United States)

^b MISSOURI UNIVERSITY OF SCIENCE AND TECHNOLOGY   (United States)

^c NCR CORPORATION   (United States)

^d UNIVERSITY OF L'AQUILA   (Italy)

Author keywords

DC power bus design; Decoupling capacitor location; High speed digital design; Local decoupling; Mutual inductance; SMT decoupling capacitors

Indexed keywords

DECOUPLING CAPACITORS;

BUSBARS; CAPACITORS; MAGNETIC FLUX; MATHEMATICAL MODELS; MULTILAYERS; SIGNAL INTERFERENCE; SPURIOUS SIGNAL NOISE; SURFACE MOUNT TECHNOLOGY;

PRINTED CIRCUIT BOARDS;

EID: 0035519401     PISSN: 00189375     EISSN: None     Source Type: Journal    
DOI: 10.1109/15.974639     Document Type: Article

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