Hybrid analytical modeling method for split power bus in multilayered package

IEEE Transactions on Electromagnetic Compatibility

Volumn 48, Issue 1, 2006, Pages 82-94

  Jeong, Youchul ^a   Lu, Albert Chee W ^b   Wai, Lai Lai ^b   Fan, Wei ^b   Lok, Boon K ^b   Park, Hyunjeong ^a   Kim, Joungho ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^b SINGAPORE INSTITUTE OF MANUFACTURING TECHNOLOGY   (Singapore)

Author keywords

Multilayered package substrate; Resonant cavity model; Segmentation method; Simultaneous switching noise (SSN); Split power bus

Indexed keywords

CAVITY RESONATORS; EQUIVALENT CIRCUITS; FREQUENCY DOMAIN ANALYSIS; MATHEMATICAL MODELS; SUBSTRATES; TIME DOMAIN ANALYSIS;

HYBRID ANALYTICAL MODELING; MULTILAYERED PACKAGE SUBSTRATE; RESONANT CAVITY MODEL; SEGMENTATION METHOD; SIMULTANEOUS SWITCHING NOISE (SSN); SPLIT POWER BUS;

POWER ELECTRONICS;

EID: 33645818961     PISSN: 00189375     EISSN: None     Source Type: Journal    
DOI: 10.1109/TEMC.2006.870701     Document Type: Article

References (27)

1. R. R. Tummala, E. J. Rymaszewski, and A. G. Klopfenstein, Microelectronics Packaging Handbook, 2nd ed., New York: Chapman & Hall, 1997, part I, ch. 3.
2. R. R. Tummala et al., "The SOP for miniaturized, mixed-signal computing, communication, and consumer systems of the next decade," IEEE Trans. Antennas Propag., vol. 27, no. 2, pp. 250-2672, May 2004.
3. H. Sasaki, et al., "Electromagnetic interference (EMI) issues for mixed-signal system-on-package (SOP)," in Proc. IEEE Electronic Components and Technology, 2004, pp. 1437-1441.
4. T. Sudo, H. Sasaki, N. Masuda, and J. L. Drewniak, "Electromagnetic interference (EMI) of system-on-package (SOP)," IEEE Trans. Antennas Propag, vol. 27, no. 2, pp. 304-314, May 2004.
5. H. Kim et al., "Significant reduction of power/ground inductive impedance and simultaneous switching noise by using embedded film capacitor," in Proc. IEEE Topical Meeting Electrical Performance of Electronic Packaging, Oct. 2003, pp. 129-132.
6. H. Kim, B. K. Sun, and J. Kim, "Suppression of GHz range power/ground inductive impedance and simultaneous switching noise using embedded film capacitors in multilayer packages and PCBs," IEEE Microw. Wireless Compon. Lett., vol. 14, no. 2, pp. 71-73, Feb. 2004.
7. P. Heydari and M. Pedram, "Analysis of jitter due to power-supply noise in phase-locked loops," in Proc. IEEE Custom Integrated Circuit Conf., 2000, pp. 443-446.
8. P. Heydari and M. Pedram, "Jitter-induced power/ground noise in CMOS PLLs: A design perspective," in Proc. IEEE Custom Integrated Circuit Conf., 2001, pp. 209-213.
9. H. H. Wu, J. W. Meyer, K. Lee, and A. Barber, "Accurate power supply and ground plane pair models," in Proc. IEEE Topical Meeting on Electrical Performance of Electronic Packaging, Oct. 26-28, 1998, pp. 163-166.
10. I. Novak, "Reducing simultaneous switching noise and EMI on ground/ power planes by dissipative edge termination," IEEE Trans. Antennas Propag, vol. 22, no. 3, pp. 274-283, Aug. 1999.
11. S. Van den Berghe, F. Olyslager, D. De Zutter, J. De Moerloose, and W. Temmerman, "Study of the ground bounce caused by power plane resonances," IEEE Trans. Electromagn. Compat., vol. 40, no. 2, pp. 111-119, May 1998.
12. Y. Ji and T. H. Hubing, "EMAP5: A 3-D hybrid FEM/MOM code," Appl. Computat. Electromagn. Soc. J., vol. 15, no. 1, pp. 1-12, Mar. 2000.
13. I. Novak, "Accuracy considerations of power-ground plane models," in Proc. IEEE Topical Meeting Electrical Performance of Electronic Packaging, Oct. 1999, pp. 153-156.
14. G. T. Lei, R. W. Techentin, and B. K. Gilbert, "High-frequency characterization of power/ground-plane structures," IEEE Trans. Microw. Theory Tech., vol. 47, no. 2, pp. 562-569, May 1999.
15. M. Xu and T. H. Hubing, "Estimating the power bus impedance of printed circuit boards with embedded capacitance," IEEE Trans. Antennas Propag, vol. 25, no. 3, pp. 424-432, Aug. 2002.
16. Z. L. Wang, O. Wada, Y. Toyota, and R. Koga, "Convergence acceleration and accuracy improvement in power bus impedance calculation with a fast algorithm using cavity modes," IEEE Trans. Electromagn. Compat., vol. 47, no. 1, pp. 2-9, Feb. 2005.
17. T. Okoshi, Planar Circuits for Microwaves and Lightwaves. Munich, Germany: Springer-Verlag, 1985, ch. 2.
18. T. Okoshi, Y. Uehara, and T. Takeuchi, "The segmentation method - An approach to the analysis of microwave planar circuits," IEEE Trans. Microw. Theory Tech., vol. 24, no. 10, pp. 662-668, Oct. 1976.
19. R. Chadha and K. C. Gupta, "Segmentation method using impedance matrices for analysis of planar microwave circuits," IEEE Trans. Microw. Theory Tech., vol. 29, no. 1, pp. 71-74, Jan. 1981.
20. R. Sorrentino, "Planar circuits, waveguide models, and segmentation method," IEEE Trans. Microw. Theory Tech., vol. 33, no. 10, pp. 1057-1066, Oct. 1985.
21. Z. L. Wang, O. Wada, Y. Toyota, and R. Koga, "Modeling of gapped power bus structures for isolation using cavity modes and segmentation," IEEE Trans. Electromagn. Compat., vol. 47, no. 2, pp. 210-218, May 2005.
22. L. Zhang, B. Archambeault, S. Conner, J. L. Knighten, J. Fan, N. W. Smith, R. Alexander, R. E. DuBroff, and J. L. Drewniak, "A circuit approach to model narrow slot structures in a power bus," in Proc. IEEE Int. Symp. Electromagnetic Compatibility, vol. 2, Aug. 2004, pp. 401-406.
23. D. Homentcovschi, A. Manolescu, A. M. Manolescu, and L. Kreindler, "An analytical solution for the coupled stripline-like microstrip line problem," IEEE Trans. Microw. Theory Tech., vol. 36, no. 6, pp. 1002-1007, Jun. 1998.
24. K. G. Gupta, Microstrip Lines and Slotlines. Norwood, MA: Artech House, 1996, ch. 8.
25. N. Na, J. Choi, S. Chun, M. Swaminathan, and J. Srinivasan, "Modeling and transient simulation of planes in electric package," IEEE Trans. Antennas Propag, vol. 23, no. 3, pp. 340-352, Aug. 2000.
26. D. M. Pozar, Microwave Engineering. New York: Wiley, 1998, ch. 4.
27. H. W. Johnson and M. Graham, High-Speed Digital Design - A Hand Book of Back Magic. Englewood Cliffs, NJ: Prentice Hall, 1993, ch. 7.