-
1
-
-
52649164042
-
Software-controlled priority characterization of POWER5 processor
-
June
-
C. Boneti, F. J. Cazorla, R. Gioiosa, A. Buyuktosunoglu, C.-Y. Cher, and M. Valero. Software-controlled priority characterization of POWER5 processor. In Proceedings of the International Symposium on Computer Architecture (ISCA), pages 415-426, June 2008.
-
(2008)
Proceedings of the International Symposium on Computer Architecture (ISCA)
, pp. 415-426
-
-
Boneti, C.1
Cazorla, F.J.2
Gioiosa, R.3
Buyuktosunoglu, A.4
Cher, C.-Y.5
Valero, M.6
-
3
-
-
33744824945
-
Predictable performance in SMT processors: Synergy between the OS and SMTs
-
July
-
F. J. Cazorla, P. M. W. Knijnenburg, R. Sakellariou, E. Fernández, A. Ramirez, and M. Valero. Predictable performance in SMT processors: Synergy between the OS and SMTs. IEEE Transactions on Computers, 55(7):785-799, July 2006.
-
(2006)
IEEE Transactions on Computers
, vol.55
, Issue.7
, pp. 785-799
-
-
Cazorla, F.J.1
Knijnenburg, P.M.W.2
Sakellariou, R.3
Fernández, E.4
Ramirez, A.5
Valero, M.6
-
4
-
-
21644443801
-
Dynamically controlled resource allocation in SMT processors
-
Dec.
-
F. J. Cazorla, A. Ramirez, M. Valero, and E. Fernandez. Dynamically controlled resource allocation in SMT processors. In Proceedings of the 37th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), pages 171-182, Dec. 2004.
-
(2004)
Proceedings of the 37th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)
, pp. 171-182
-
-
Cazorla, F.J.1
Ramirez, A.2
Valero, M.3
Fernandez, E.4
-
5
-
-
4644223464
-
QoS for high-performance SMT processors in embedded systems
-
July
-
F. J. Cazorla, A. Ramirez, M. Valero, P. M. W. Knijnenburg, R. Sakellariou, and E. Fernández. QoS for high-performance SMT processors in embedded systems. IEEE Micro, 24(4):24-31, July 2004.
-
(2004)
IEEE Micro
, vol.24
, Issue.4
, pp. 24-31
-
-
Cazorla, F.J.1
Ramirez, A.2
Valero, M.3
Knijnenburg, P.M.W.4
Sakellariou, R.5
Fernández, E.6
-
6
-
-
21244474546
-
Predicting inter-thread cache contention on a chip-multiprocessor architecture
-
Feb.
-
D. Chandra, F. Guo, S. Kim, and Y. Solihin. Predicting inter-thread cache contention on a chip-multiprocessor architecture. In Proceedings of the Eleventh International Symposium on High Performance Computer Architecture (HPCA), pages 340-351, Feb. 2005.
-
(2005)
Proceedings of the Eleventh International Symposium on High Performance Computer Architecture (HPCA)
, pp. 340-351
-
-
Chandra, D.1
Guo, F.2
Kim, S.3
Solihin, Y.4
-
8
-
-
67650091545
-
Priority Based Simultaneous Multi-Threading
-
Dec. United States Patent No. 6,658,447 B2
-
E. Cota-Robles. Priority Based Simultaneous Multi-Threading, Dec. 2003. United States Patent No. 6,658,447 B2.
-
(2003)
-
-
Cota-Robles, E.1
-
11
-
-
47249094055
-
System-level performance metrics for multi-program workloads
-
May/June
-
S. Eyerman and L. Eeckhout. System-level performance metrics for multi-program workloads. IEEE Micro, 28(3):42-53, May/June 2008.
-
(2008)
IEEE Micro
, vol.28
, Issue.3
, pp. 42-53
-
-
Eyerman, S.1
Eeckhout, L.2
-
14
-
-
85010294164
-
Fairness enforcement in switch on event multithreading
-
Sept.
-
R. Gabor, S. Weiss, and A. Mendelson. Fairness enforcement in switch on event multithreading. ACM Transactions on Architecture and Code Optimization (TACO), 4(3):34, Sept. 2007.
-
(2007)
ACM Transactions on Architecture and Code Optimization (TACO)
, vol.4
, Issue.3
, pp. 34
-
-
Gabor, R.1
Weiss, S.2
Mendelson, A.3
-
15
-
-
55749111443
-
-
IBM, Nov.
-
B. Gibbs, B. Atyam, F. Berres, B. Blanchard, L. Castillo, P. Coelho, N. Guerin, L. Liu, C. D. Maciel, C. Sosa, and C. Thirumalai. Advanced POWER Virtualization on IBM eServer p5 Servers: Architecture and Performance Considerations. IBM, Nov. 2005.
-
(2005)
Advanced POWER Virtualization on IBM EServer P5 Servers: Architecture and Performance Considerations
-
-
Gibbs, B.1
Atyam, B.2
Berres, F.3
Blanchard, B.4
Castillo, L.5
Coelho, P.6
Guerin, N.7
Liu, L.8
Maciel, C.D.9
Sosa, C.10
Thirumalai, C.11
-
18
-
-
0013229812
-
-
Technical report, University of Washington
-
S. Parekh, S. Eggers, H. Levy, and J. Lo. Thread-sensitive scheduling for SMT processors. Technical report, University of Washington, 2000.
-
(2000)
Thread-sensitive Scheduling for SMT Processors
-
-
Parekh, S.1
Eggers, S.2
Levy, H.3
Lo, J.4
-
21
-
-
57749185053
-
Runahead threads to improve SMT performance
-
Feb.
-
T. Ramirez, A. Pajuelo, O. J. Santana, and M. Valero. Runahead threads to improve SMT performance. In Proceedings of the Fourteenth International Symposium on High-Performance Computer Architecture (HPCA), pages 149-158, Feb. 2008.
-
(2008)
Proceedings of the Fourteenth International Symposium on High-Performance Computer Architecture (HPCA)
, pp. 149-158
-
-
Ramirez, T.1
Pajuelo, A.2
Santana, O.J.3
Valero, M.4
-
22
-
-
10444263677
-
Architectural support for enhanced SMT job scheduling
-
Sept.
-
A. Settle, J. Kihm, A. Janiszewski, and D. Connors. Architectural support for enhanced SMT job scheduling. In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT), pages 63-73, Sept. 2004.
-
(2004)
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT)
, pp. 63-73
-
-
Settle, A.1
Kihm, J.2
Janiszewski, A.3
Connors, D.4
-
23
-
-
0036953769
-
Automatically characterizing large scale program behavior
-
Oct.
-
T. Sherwood, E. Perelman, G. Hamerly, and B. Calder. Automatically characterizing large scale program behavior. In Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pages 45-57, Oct. 2002.
-
(2002)
Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)
, pp. 45-57
-
-
Sherwood, T.1
Perelman, E.2
Hamerly, G.3
Calder, B.4
-
31
-
-
0029666641
-
Exploiting choice: Instruction fetch and issue on an implementable simultaneous multithreading processor
-
May
-
D. M. Tullsen, S. J. Eggers, J. S. Emer, H. M. Levy, J. L. Lo, and R. L. Stamm. Exploiting choice: Instruction fetch and issue on an implementable simultaneous multithreading processor. In Proceedings of the 23rd Annual International Symposium on Computer Architecture (ISCA), pages 191-202, May 1996.
-
(1996)
Proceedings of the 23rd Annual International Symposium on Computer Architecture (ISCA)
, pp. 191-202
-
-
Tullsen, D.M.1
Eggers, S.J.2
Emer, J.S.3
Levy, H.M.4
Lo, J.L.5
Stamm, R.L.6
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