Software-controlled priority characterization of POWERS processor

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2008, Pages 415-426

  Boneti, Carlos ^a   Cazorla, Francisco J ^b   Gioiosa, Roberto ^b   Buyuktosunoglu, Alper ^c   Cher, Chen Yong ^c   Valero, Mateo ^a,b  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^b BARCELONA SUPERCOMPUTING CENTER   (Spain)

^c IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER SCIENCE; COMPUTER SYSTEMS; COMPUTERS; MECHANISMS; THROUGHPUT;

CASE STUDIES; DUAL CORES; EXECUTION TIME; INSTRUCTION-LEVEL PARALLELISM; INTERNATIONAL SYMPOSIUM; MULTI-THREADED; PERFORMANCE CHARACTERIZATION; PERFORMANCE METRICS; PRIORITIZATION; PROCESSOR PERFORMANCE; SECOND-LEVEL; SOFTWARE PLATFORMS; SOFTWARE-BASED; SYNTHETIC WORKLOADS; THREAD-LEVEL PARALLELISM;

COMPUTER SOFTWARE;

EID: 52649164042     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCA.2008.8     Document Type: Conference Paper

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