-
1
-
-
52649164042
-
Software-controlled priority characterization of POWER5 processor
-
June
-
C. Boneti, F. J. Cazorla, R. Gioiosa, A. Buyuktosunoglu, C.-Y. Cher, and M. Valero. Software-controlled priority characterization of POWER5 processor. In ISCA, pages 415-426, June 2008.
-
(2008)
ISCA
, pp. 415-426
-
-
Boneti, C.1
Cazorla, F.J.2
Gioiosa, R.3
Buyuktosunoglu, A.4
Cher, C.-Y.5
Valero, M.6
-
2
-
-
33744824945
-
Predictable performance in SMT processors: Synergy between the OS and SMTs
-
July
-
F. J. Cazorla, P. M. W. Knijnenburg, R. Sakellariou, E. Fernández, A. Ramirez, and M. Valero. Predictable performance in SMT processors: Synergy between the OS and SMTs. IEEE Transactions on Computers, 55(7):785-799, July 2006.
-
(2006)
IEEE Transactions on Computers
, vol.55
, Issue.7
, pp. 785-799
-
-
Cazorla, F.J.1
Knijnenburg, P.M.W.2
Sakellariou, R.3
Fernández, E.4
Ramirez, A.5
Valero, M.6
-
3
-
-
21644443801
-
Dynamically controlled resource allocation in SMT processors
-
Dec
-
F. J. Cazorla, A. Ramirez, M. Valero, and E. Fernandez. Dynamically controlled resource allocation in SMT processors. In MICRO, pages 171-182, Dec. 2004.
-
(2004)
MICRO
, pp. 171-182
-
-
Cazorla, F.J.1
Ramirez, A.2
Valero, M.3
Fernandez, E.4
-
4
-
-
4644223464
-
QoS for high-performance SMT processors in embedded systems
-
July
-
F. J. Cazorla, A. Ramirez, M. Valero, P. M. W. Knijnenburg, R. Sakellariou, and E. Fernández. QoS for high-performance SMT processors in embedded systems. IEEE Micro, 24(4):24-31, July 2004.
-
(2004)
IEEE Micro
, vol.24
, Issue.4
, pp. 24-31
-
-
Cazorla, F.J.1
Ramirez, A.2
Valero, M.3
Knijnenburg, P.M.W.4
Sakellariou, R.5
Fernández, E.6
-
5
-
-
33845901233
-
Learning-based SMT processor resource distribution via hill-climbing
-
June
-
S. Choi and D. Yeung. Learning-based SMT processor resource distribution via hill-climbing. In ISCA, pages 239-250, June 2006.
-
(2006)
ISCA
, pp. 239-250
-
-
Choi, S.1
Yeung, D.2
-
6
-
-
4644226058
-
Microarchitecture optimizations for exploiting memory-level parallelism
-
June
-
Y. Chou, B. Fahs, and S. Abraham. Microarchitecture optimizations for exploiting memory-level parallelism. In ISCA, pages 76-87, June 2004.
-
(2004)
ISCA
, pp. 76-87
-
-
Chou, Y.1
Fahs, B.2
Abraham, S.3
-
7
-
-
67650091545
-
Priority Based Simultaneous Multi-Threading
-
Dec, United States Patent No. 6,658,447 B2
-
E. Cota-Robles. Priority Based Simultaneous Multi-Threading, Dec. 2003. United States Patent No. 6,658,447 B2.
-
(2003)
-
-
Cota-Robles, E.1
-
8
-
-
0031340339
-
ProfileMe: Hardware support for instruction-level profiling on out-of-order processors
-
Dec
-
J. Dean, J. E. Hicks, C. A. Waldspurger, W. E. Weihl, and G. Chrysos. ProfileMe: Hardware support for instruction-level profiling on out-of-order processors. In MICRO, Dec. 1997.
-
(1997)
MICRO
-
-
Dean, J.1
Hicks, J.E.2
Waldspurger, C.A.3
Weihl, W.E.4
Chrysos, G.5
-
10
-
-
34547699255
-
A memory-level parallelism aware fetch policy for SMT processors
-
Feb
-
S. Eyerman and L. Eeckhout. A memory-level parallelism aware fetch policy for SMT processors. In HPCA, pages 240-249, Feb. 2007.
-
(2007)
HPCA
, pp. 240-249
-
-
Eyerman, S.1
Eeckhout, L.2
-
11
-
-
47249094055
-
System-level performance metrics for multi-program workloads
-
May/June
-
S. Eyerman and L. Eeckhout. System-level performance metrics for multi-program workloads. IEEE Micro, 28(3):42-53, May/June 2008.
-
(2008)
IEEE Micro
, vol.28
, Issue.3
, pp. 42-53
-
-
Eyerman, S.1
Eeckhout, L.2
-
12
-
-
34249813667
-
A performance counter architecture for computing accurate CPI components
-
Oct
-
S. Eyerman, L. Eeckhout, T. Karkhanis, and J. E. Smith. A performance counter architecture for computing accurate CPI components. In ASPLOS, pages 175-184, Oct. 2006.
-
(2006)
ASPLOS
, pp. 175-184
-
-
Eyerman, S.1
Eeckhout, L.2
Karkhanis, T.3
Smith, J.E.4
-
14
-
-
84991726534
-
Interaction cost and shotgun profiling
-
Sept
-
B. A. Fields, R. Bodik, M. D. Hill, and C. J. Newburn. Interaction cost and shotgun profiling. ACM Transactions on Architecture and Code Optimization, 1(3):272-304, Sept. 2004.
-
(2004)
ACM Transactions on Architecture and Code Optimization
, vol.1
, Issue.3
, pp. 272-304
-
-
Fields, B.A.1
Bodik, R.2
Hill, M.D.3
Newburn, C.J.4
-
15
-
-
85010294164
-
Fairness enforcement in switch on event multithreading
-
Sept
-
R. Gabor, S. Weiss, and A. Mendelson. Fairness enforcement in switch on event multithreading. ACM Transactions on Architecture and Code Optimization (TACO), 4(3):34, Sept. 2007.
-
(2007)
ACM Transactions on Architecture and Code Optimization (TACO)
, vol.4
, Issue.3
, pp. 34
-
-
Gabor, R.1
Weiss, S.2
Mendelson, A.3
-
17
-
-
4644299010
-
A first-order superscalar processor model
-
June
-
T. S. Karkhanis and J. E. Smith. A first-order superscalar processor model. In ISCA, pages 338-349, June 2004.
-
(2004)
ISCA
, pp. 338-349
-
-
Karkhanis, T.S.1
Smith, J.E.2
-
18
-
-
84962144701
-
Balancing throughput and fairness in SMT processors
-
Nov
-
K. Luo, J. Gummaraju, and M. Franklin. Balancing throughput and fairness in SMT processors. In ISPASS, pages 164-171, Nov. 2001.
-
(2001)
ISPASS
, pp. 164-171
-
-
Luo, K.1
Gummaraju, J.2
Franklin, M.3
-
19
-
-
33846529179
-
Performance monitoring on the POWER5 microprocessor
-
L. K. John and L. Eeckhout, editors, CRC Press
-
A. Mericas. Performance monitoring on the POWER5 microprocessor. In L. K. John and L. Eeckhout, editors, Performance Evaluation and Benchmarking, pages 247-266. CRC Press, 2006.
-
(2006)
Performance Evaluation and Benchmarking
, pp. 247-266
-
-
Mericas, A.1
-
20
-
-
33845874613
-
A case for MLP-aware cache replacement
-
June
-
M. K. Qureshi, D. N. Lynch, O. Mutlu, and Y. N. Patt. A case for MLP-aware cache replacement. In ISCA, pages 167-177, June 2006.
-
(2006)
ISCA
, pp. 167-177
-
-
Qureshi, M.K.1
Lynch, D.N.2
Mutlu, O.3
Patt, Y.N.4
-
21
-
-
84968718478
-
The impact of resource partitioning on SMT processors
-
Sept
-
S. E. Raasch and S. K. Reinhardt. The impact of resource partitioning on SMT processors. In PACT , pages 15-26, Sept. 2003.
-
(2003)
PACT
, pp. 15-26
-
-
Raasch, S.E.1
Reinhardt, S.K.2
-
22
-
-
0036953769
-
Automatically characterizing large scale program behavior
-
Oct
-
T. Sherwood, E. Perelman, G. Hamerly, and B. Calder. Automatically characterizing large scale program behavior. In ASPLOS, pages 45-57, Oct. 2002.
-
(2002)
ASPLOS
, pp. 45-57
-
-
Sherwood, T.1
Perelman, E.2
Hamerly, G.3
Calder, B.4
-
23
-
-
0034443570
-
Symbiotic jobscheduling for simultaneous multithreading processor
-
Nov
-
A. Snavely and D. M. Tullsen. Symbiotic jobscheduling for simultaneous multithreading processor. In ASPLOS, pages 234-244, Nov. 2000.
-
(2000)
ASPLOS
, pp. 234-244
-
-
Snavely, A.1
Tullsen, D.M.2
-
24
-
-
0036038691
-
Symbiotic jobscheduling with priorities for a simultaneous multithreading processor
-
June
-
A. Snavely, D. M. Tullsen, and G. Voelker. Symbiotic jobscheduling with priorities for a simultaneous multithreading processor. In SIGMETRICS, pages 66-76, June 2002.
-
(2002)
SIGMETRICS
, pp. 66-76
-
-
Snavely, A.1
Tullsen, D.M.2
Voelker, G.3
-
27
-
-
0035696665
-
Handling long-latency loads in a simultaneous multithreading processor
-
Dec
-
D. M. Tullsen and J. A. Brown. Handling long-latency loads in a simultaneous multithreading processor. In MICRO, pages 318-327, Dec. 2001.
-
(2001)
MICRO
, pp. 318-327
-
-
Tullsen, D.M.1
Brown, J.A.2
-
28
-
-
0029666641
-
Exploiting choice: Instruction fetch and issue on an implementable simultaneous multithreading processor
-
May
-
D. M. Tullsen, S. J. Eggers, J. S. Emer, H. M. Levy, J. L. Lo, and R. L. Stamm. Exploiting choice: Instruction fetch and issue on an implementable simultaneous multithreading processor. In ISCA, pages 191-202, May 1996.
-
(1996)
ISCA
, pp. 191-202
-
-
Tullsen, D.M.1
Eggers, S.J.2
Emer, J.S.3
Levy, H.M.4
Lo, J.L.5
Stamm, R.L.6
-
29
-
-
0029200683
-
Simultaneous multithreading: Maximizing on-chip parallelism
-
June
-
D. M. Tullsen, S. J. Eggers, and H. M. Levy. Simultaneous multithreading: Maximizing on-chip parallelism. In ISCA, pages 392-403, June 1995.
-
(1995)
ISCA
, pp. 392-403
-
-
Tullsen, D.M.1
Eggers, S.J.2
Levy, H.M.3
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