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Volumn 24, Issue 4, 2004, Pages 24-31

QoS for high-performance SMT processors in embedded systems

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER OPERATING SYSTEMS; EMBEDDED SYSTEMS; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; QUALITY OF SERVICE; REAL TIME SYSTEMS; REQUIREMENTS ENGINEERING; RESOURCE ALLOCATION;

EID: 4644223464     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2004.37     Document Type: Article
Times cited : (44)

References (13)
  • 1
    • 4644337446 scopus 로고    scopus 로고
    • Philips powers up for video
    • Nov. 3
    • T.R. Halfhill, "Philips Powers Up for Video," Microprocessor Report, no. 168, Nov. 3, 2003.
    • (2003) Microprocessor Report , Issue.168
    • Halfhill, T.R.1
  • 2
    • 4644332883 scopus 로고    scopus 로고
    • Multithreaded technologies disclosed at MPF
    • Nov. 10
    • M. Levy, "Multithreaded Technologies Disclosed at MPF," Microprocessor Report, no. 168, Nov. 10, 2003.
    • (2003) Microprocessor Report , Issue.168
    • Levy, M.1
  • 6
    • 4644317965 scopus 로고    scopus 로고
    • Approaching a smart sharing of resources in SMT processors
    • June
    • F.J. Cazorla et al., "Approaching a Smart Sharing of Resources in SMT Processors," Proc. Workshop Complexity-Effective Design (WCED), June 2004; http://www.ece.rochester.edu/~albonesi/wced04/.
    • (2004) Proc. Workshop Complexity-Effective Design (WCED)
    • Cazorla, F.J.1
  • 9
    • 0035696665 scopus 로고    scopus 로고
    • Handling long-latency loads in a simultaneous multithreaded processor
    • IEEE CS Press
    • D. Tullsen and J. Brown, "Handling Long-Latency Loads in a Simultaneous Multithreaded Processor," Proc. 34th Int'l Symp. Microarchitecture (Micro-34), IEEE CS Press, 2001, pp. 318-327.
    • (2001) Proc. 34th Int'l Symp. Microarchitecture (Micro-34) , pp. 318-327
    • Tullsen, D.1    Brown, J.2
  • 11
    • 0029666641 scopus 로고    scopus 로고
    • Exploiting choice: Instruction fetch and issue on an implementable simultaneous multithreading processor
    • D. Tullsen et al., "Exploiting choice: Instruction fetch and issue on an implementable simultaneous multithreading processor". Proc. 23rd Int'l Symp. on Computer Architecture (ISCA-23), 1996, pp. 191-202.
    • (1996) Proc. 23rd Int'l Symp. on Computer Architecture (ISCA-23) , pp. 191-202
    • Tullsen, D.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.