Runahead threads to improve SMT performance

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2008, Pages 149-158

  Ramírez, Tanausú ^a   Pajuelo, Alex ^a   Santana, Oliverio J ^b   Valero, Mateo ^a,c  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^b UNIVERSITY OF LAS PALMAS DE GRAN CANARIA   (Spain)

^c BARCELONA SUPERCOMPUTING CENTER   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTERS; RAT CONTROL; SURFACE MOUNT TECHNOLOGY;

AVERAGE THROUGHPUTS; CRITICAL RESOURCES; DYNAMIC RESOURCE CONTROLS; DYNAMIC RESOURCE SCHEDULING; FETCH POLICIES; MEMORY OPERATIONS; MINIMAL RESOURCES; MULTITHREADED; PERFORMANCE DEGRADATIONS; PREFETCH; REGISTER FILES; RESOURCE CONTENTIONS; RESOURCE INTENSIVES; SMT ARCHITECTURES; SMT PROCESSORS;

COMPUTER ARCHITECTURE;

EID: 57749185053     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2008.4658635     Document Type: Conference Paper

References (22)

1. F. J. Cazorla, A. Ramirez, E. Fernandez, and M. Valero. Dynamically controlled resource allocation in smt processors. In Int. Symposium on Microarchitecture (MICRO-37), pages 171-182, 2004.
2. R. S. Chappell, J. Stark, S. K. Reinhardt, Y. N. Patt, and S. P. Kim. Simultaneous subordinate microthreading (ssmt). Int. Symposium on Computer Architecture (ISCA-26), 00, 1999.
3. S. Choi and D. Yeung. Learning-based smt processor resource distribution via hill-climbing. In Int. Symposium on Computer Architecture (ISCA-33), pages 239-251, Washington, DC, USA, 2006.
4. J. D. Collins, D. M. Tullsen, H. Wang, and J. P. Shen. Dynamic speculative precomputation. Int. Symposium on Microarchitecture (MICRO-34), 2001.
5. J. Dundas and T. Mudge. Improving data cache performance by pre-executing instructions under a cache miss. In Int. Conference on Supercomputing (ICS-11), NY, USA, 1997.
6. R. Gonçalves, E. Ayguade, M. Valero, and P. Navaux. Performance evaluation of decoding and dispatching stages in simultaneous multithreaded architectures. SBAC-PAD, 2001.
7. R. Gonzalez and M. Horowitz. Energy dissipation in general purpose microprocessors. IEEE J. Solid-State Circuits, pages Vol. 31, No. 9, 1996.
8. S. Hily and A. Seznec. Contention on 2nd level cache may limit the effectiveness of simultaneous multithreading. Technical Report PI-1086, INRIA, 1997.
9. K. Luo, J. Gummaraju, and M. Franklin. Balancing throughput and fairness in smt processors. In ISPASS, Tucson - AZ, USA, 2001.
10. O. Mutlu, H. Kim, and Y. N. Patt. Techniques for efficient processing in runahead execution engines. In International Symposium on Computer Architecture (ISCA-32), pages 370-381, 2005.
11. O. Mutlu, J. Stark, C. Wilkerson, and Y. N. Patt. Runahead execution: An alternative to very large instruction windows for out-of-order processors. In Int. Symposium on High-Performance Computer Architecture (HPCA-9), page 129, Washington, DC, USA, 2003.
12. A. Roth and G. S. Sohi. Speculative data-driven multithreading. Int. Symposium on High-Performance Computer Architecture (HPCA-7), 2001.
13. J. Sharkey and D. Ponomarev. An l2-miss-driven early register deallocation for smt processors. In Int. Conference on Supercomputing (ICS-21), pages 138-147, NY, USA, 2007.
14. T. Sherwood, E. Perelman, and B. Calder. Basic block distribution analysis to nd periodic behavior and simulation points in applications. In Parallel Architectures and Compilation Techniques (PACT-10), pages 3-14, Barcelona, Spain, 2001.
15. E. Stijn and E. Lieven. A memory-level parallelism aware fetch policy for smt processors. In Int. Symposium on High-Performance Computer Architecture (HPCA-13), 2007.
16. D. M. Tullsen. Simulation and modeling of a simultaneous multithreading processor. In Int. Annual Computer Measurement Group Conference, pages 819-828, 1996.
17. D. M. Tullsen and J. A. Brown. Handling long-latency loads in a simultaneous multithreading processor. In Int. Symposium on Microarchitecture, 2007 (MICRO-34), Washington, DC, USA, 2001.
18. D. M. Tullsen, S. J. Eggers, J. S. Emer, H. M. Levy, J. L. Lo, and R. L. Stamm. Exploiting choice: instruction fetch and issue on an implementable simultaneous multithreading processor. In Int. Symposium on Computer Architecture (ISCA-23), pages 191-202, New York, NY, USA, 1996.
19. J. Vera, F. J. Cazorla, A. Pajuelo, O. J. Santana, E. Fernandez, and M. Valero. Fame: Fairly measuring multithreaded architectures. In Parallel Architectures and Compilation Techniques (PACT-16), 2007.
20. S. Wallace, B. Calder, and D. M. Tullsen. Threaded multiple path execution. In Int. Symposium on Computer Architecture (ISCA-25), pages 238-249, Washington, DC, USA, 1998.
21. W. Yamamoto and M. Nemirovsky. Increasing superscalar performance through multistreaming. In Parallel Architectures and Compilation Techniques (PACT-4), pages 49-58, Manchester, UK, 1995.
22. W. Zhang, D. M. Tullsen, and B. Calder. Accelerating and adapting precomputation threads for efficient prefetching. In Int. Symposium on High-Performance Computer Architecture (HPCA-13), 2007.