Chip integration methodology for the IBM S/390 G5 and G6 custom microprocessors

IBM Journal of Research and Development

Volumn 43, Issue 5, 1999, Pages 681-706

  Averill III, R M ^a   Barkley, K G ^a   Bowen, M A ^a   Camporese, P J ^a   Dansky, A H ^a   Hatch, R F ^a   Hoffman, D E ^a   Mayo, M D ^a   McCabe, S A ^a   McNamara, T G ^a   McPherson, T J ^a   Northrop, G A ^a   Sigal, L ^a   Smith, H H ^a   Webber, D A ^a   Williams, P M ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS; TRANSISTORS;

BRANCH CONTROL ELEMENT UNIT; CHIP INTEGRATION; COPPER INTERCONNECT WIRING;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0033349830     PISSN: 00188646     EISSN: None     Source Type: Journal    
DOI: 10.1147/rd.435.0681     Document Type: Article

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