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Volumn 51, Issue 6, 2007, Pages 715-731

Power-constrained high-frequency circuits for the IBM POWER6 microprocessor

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER HARDWARE; INTEGRATED CIRCUIT LAYOUT; POWER CONTROL; SILICON ON INSULATOR TECHNOLOGY;

EID: 37549008714     PISSN: 00188646     EISSN: 00188646     Source Type: Journal    
DOI: 10.1147/rd.516.0715     Document Type: Review
Times cited : (11)

References (11)
  • 1
    • 39749083510 scopus 로고    scopus 로고
    • B. Curran, B. McCredie, L. Sigal, E. Schwarz, B. Fleischer, Y. H. Chan, D. Webber, M. Vaden, and A. Goyal, 4GHz+ Low-Latency Fixed-Point and Binary Floating-Point Execution Units for the POWER6 Processor, Solid-State Circuits, 2006 IEEE ISSCC Digest of Technical Papers, February 6-9, 2006, pp. 436-437.
    • B. Curran, B. McCredie, L. Sigal, E. Schwarz, B. Fleischer, Y. H. Chan, D. Webber, M. Vaden, and A. Goyal, "4GHz+ Low-Latency Fixed-Point and Binary Floating-Point Execution Units for the POWER6 Processor," Solid-State Circuits, 2006 IEEE ISSCC Digest of Technical Papers, February 6-9, 2006, pp. 436-437.
  • 4
    • 37549057592 scopus 로고    scopus 로고
    • D. W. Plass and Y. H. Chan, IBM POWER6 SRAM Arrays, IBM J. Res. & Dev. 51, No. 6, 747-756 (2007, this issue).
    • D. W. Plass and Y. H. Chan, "IBM POWER6 SRAM Arrays," IBM J. Res. & Dev. 51, No. 6, 747-756 (2007, this issue).
  • 5
    • 37549056552 scopus 로고    scopus 로고
    • R. Berridge, R. M. Averill III, A. E. Barish, M. A. Bowen, P. J. Camporese, J. DiLullo, P. E. Dudley, et al., IBM POWER6 Microprocessor Physical Design and Design Methodology, IBM J. Res. & Dev. 51, No. 6, 685-714 (2007, this issue).
    • R. Berridge, R. M. Averill III, A. E. Barish, M. A. Bowen, P. J. Camporese, J. DiLullo, P. E. Dudley, et al., "IBM POWER6 Microprocessor Physical Design and Design Methodology," IBM J. Res. & Dev. 51, No. 6, 685-714 (2007, this issue).
  • 7
    • 37549033569 scopus 로고    scopus 로고
    • M. G. R. Thomson, P. J. Restle, and N. K. James, A 5GHz Duty-Cycle Correcting Clock Distribution Network for. the POWER6 Microprocessor, Solid-State Circuits, 2006 IEEE ISSCC Digest of Technical Papers, February 6-9, 2006, pp. 1522-1529.4
    • M. G. R. Thomson, P. J. Restle, and N. K. James, "A 5GHz Duty-Cycle Correcting Clock Distribution Network for. the POWER6 Microprocessor," Solid-State Circuits, 2006 IEEE ISSCC Digest of Technical Papers, February 6-9, 2006, pp. 1522-1529.4
  • 11
    • 34548817261 scopus 로고    scopus 로고
    • J. Friedrich, B. McCredie, N. James, B. Huott, B. Curran, E. Fluhr, G. Mittal, et al., Design of POWER6™ Microprocessor, Proceedings of the International Solid-State Circuits Conference (ISSCC), San Francisco, CA, February 11-15, 2007, Solid-State Circuits, 2007 IEEE ISSCC Digest of Technical Papers.
    • J. Friedrich, B. McCredie, N. James, B. Huott, B. Curran, E. Fluhr, G. Mittal, et al., "Design of POWER6™ Microprocessor," Proceedings of the International Solid-State Circuits Conference (ISSCC), San Francisco, CA, February 11-15, 2007, Solid-State Circuits, 2007 IEEE ISSCC Digest of Technical Papers.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.