A power-aware mapping approach to map IP cores onto NoCs under bandwidth and latency constraints

Transactions on Architecture and Code Optimization

Volumn 7, Issue 1, 2010, Pages

  Wang, Xiaohang ^a   Yang, Mei ^b   Jiang, Yingtao ^b   Liu, Peng ^a  

^a ZHEJIANG UNIVERSITY   (China)

^b University of Nevada Las Vegas   (United States)

Author keywords

Bandwidth and latency constraints; IP mapping; Low power; Network on chip (NoC)

Indexed keywords

BRANCH AND BOUNDS; COMPUTATION COSTS; CPU TIME; GRAPH PARTITION; IP CORE; IP MAPPING; LATENCY CONSTRAINTS; LOW POWER NETWORKS; MAPPING ALGORITHMS; MAPPING PROBLEM; MULTIMEDIA BENCHMARKS; NETWORK-ON-CHIP (NOC); NETWORK-ON-CHIP ARCHITECTURES; ON-CHIP NETWORKS; OPTIMAL RESULTS; POWER CONSUMPTION; POWER SAVINGS; POWER-AWARE; RUN TIME COMPLEXITY; TEMPLATE-BASED; TIGHTLY-COUPLED;

ALGORITHMS; BANDWIDTH; CLOSED LOOP CONTROL SYSTEMS; CONFORMAL MAPPING; NETWORK ARCHITECTURE; VLSI CIRCUITS;

GRAPH THEORY;

EID: 77952027696     PISSN: 15443566     EISSN: 15443973     Source Type: Journal    
DOI: 10.1145/1736065.1736066     Document Type: Article

References (27)

1. ASCIA, G., CATANIA, V., AND PALESI, M. 2004. Multi-objective mapping for mesh-based NoC architectures. In Proceedings of the 2nd International Conference on Hardware/Software Co-Design and System Synthesis. IEEE, Los Alamitos, CA, 182-187.
2. BERTOZZI, D., JALABERT, A., MURALI, S., TAMHANKAR, R., STERGIOU, S., BENINI, L., AND DE MICHELI, G. 2005. NoC synthesis flow for customized domain specificmultiprocessor systems-on-chip. IEEE Trans. Paral. Distrib. Syst. 16, 2, 113-129.
3. CHANG, J. M. AND PEDRAM, M. 2000. Codex-dp: Co-design of communicating systems using dynamic programming. IEEE Trans. Comput. Aid. Des. Integr. Circuits Syst. 19, 7, 732-744.
4. DALLY, W. J. AND TOWLES, B. 2001. Route packets, not wires: On-chip interconnection networks. In Proceedings of the 38th Design Automation Conference (DAC). ACM, New York, 684-689.
5. DICK, R. P., RHODES, D. L., AND WOLF, W. 1998. TGFF: Task graphs for free. In Proceedings of the 6th International Workshop on Hardware/Software Co-Design. ACM, New York, 97-101.
6. DUATO, J., YALAMANCHILI, S., AND NI, L. M. 2003. Interconnection Networks: An Engineering Approach. Morgan Kaufmann Publishers, San Francisco, CA.
7. GAREY, M. R. AND JOHNSON, D. S. 1979. Computers and Intractability: A Guide to the Theory of NP-Completeness.WH Freeman, San Francisco, CA.
8. HANSSON, A., GOOSSENS, K., AND RADULESCU, A. 2005. A unified approach to constrained mapping and routing on network-on-chip architectures. In Proceedings of the 3rd International Conference on Hardware/Software Co-Design and System Synthesis. IEEE, Los Alamitos, CA, 75-80.
9. HARMANANI, H. M. AND FARAH, R. 2008. A method for efficient mapping and reliable routing for NoC architectures with minimum bandwidth and area. In Proceedings of the Conference on Circuits and Systems and TAISA. IEEE, Los Alamitos, CA, 29-32.
10. HENDRICKSON, B. AND LELAND, R. 1995. The Chaco User's Guide: Version 2.0. Sandia National Laboratories, Albuquerque, NM.
11. HO, R.,MAI, K. W., AND HOROWITZ, M. A. 2001. The future of wires. Proc. of IEEE. 89, 4, 490-504.
12. HU, J. AND MARCULESCU, R. 2003. Energy-aware mapping for tile-based NoC architectures under performance constraints. In Proceedings of the Design Automation Conference. ACM, New York, 233-239.
13. HU, J. AND MARCULESCU, R. 2005. Energy-and performance-aware mapping for regular NoC architectures. IEEE Trans. Comput. Aid. Des. Integr. Circuits Syst. 24, 4, 551-562.
14. ITRS. 2007. International technology roadmap for semiconductors. http://www.itrs.net/Links/ 2007ITRS/Home2007.htm.
15. JANTSCH, A. AND TENHUNEN, H. 2003. Networks on Chip. Kluwer Academic Publishers, New York.
16. KODI, A. K., SARATHY, A., AND LOURI, A. 2008. Adaptive channel buffers in on-chip interconnection networks: A power and performance analysis. IEEE Trans. Comput. 57, 9, 1169-1181.
17. LIN, H., LI, X., TONG, D. AND CHENG, X. 2008. A low energy mapping and routing approach for network on chip with QoS guarantees. J. Comput. Aid. Des. Comput. Graphics. 20, 4, 425-431.
18. LU, Z., XIA, L., AND JANTSCH, A. 2008. Cluster-based simulated annealing for mapping cores onto 2D mesh networks on chip. In Proceedings of the IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. IEEE, Los Alamitos, CA, 1-6.
19. MARCON, C. A. M.,MORENO, E. I., CALAZANS, N. L. V. AND MORAES, F. G. 2007. Evaluation of algorithms for low energy mapping onto NoCs. In Proceedings of the IEEE International Symposium on Circuits and Systems. IEEE, Los Alamitos, CA, 389-392. ACM Transactions on Architecture and Code Optimization, Vol. 7, No. 1, Article 1, Publication date: April 2010.
20. MEHRAN, A., SAEIDI, S.,KHADEMZADEH, A., AND AFZALI-KUSHA, A. 2007. Spiral: A heuristic mapping algorithm for network on chip. IEICE Electron. Express 4, 15, 478-484.
21. MEINDL, J. D. 2003. Interconnect opportunities for gigascale integration. IEEE Micro. 23, 3, 28-35.
22. MURALI, S. AND DEMICHELI, G. 2004. Bandwidth-constrained mapping of cores onto NoC architectures. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition. ACM, New York, 896-901. NOXIM. Network-on-chip simulator. http://sourceforge.net/projects/noxim
23. OGRAS, U. Y., HU, J., AND MARCULESCU, R. 2005. Key research problems in NoC design: a holistic perspective. In Proceedings of the 3rd InternationalConference on Hardware/Software Co-Design and System Synthesis. IEEE, Los Alamitos, CA, 69-74.
24. PINTO, A., CARLONI, L., AND VINCENTELLI, A. 2009. A methodology for constraint-driven synthesis of on-chip communications. IEEE Trans. Comput. Aid. Des. 28, 3, 364-377.
25. SRINIVASAN, K. AND CHATHA, K. S. 2005. A technique for low energy mapping and routing in network-on-chip architectures. In Proceedings of the International Symposium on Low Power Electronics and Design. ACM, New York, 387-392.
26. WANG, H., ZHU, X., PEH, L-S., AND MALIK, S. 2002. Orion: a power-performance simulator for interconnection networks. In Proceedings of the 35th Annual International Symposium on Microarchitecture. IEEE, Los Alamitos, CA, 294-305.
27. ZHOU, W., ZHANG, Y., AND MAO, Z. 2006. Pareto-based multi-objective mapping IP cores onto NoC architectures. In Proceedings of the Asia Pacific Conference on Circuits and Systems. IEEE, Los Alamitos, CA, 331-334.