Pareto based multi-objective mapping IP Cores onto NoC architectures

IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Volumn , Issue , 2006, Pages 331-334

  Zhou, Wenbiao ^a   Zhang, Yan ^a   Mao, Zhigang ^a  

^a HARBIN INSTITUTE OF TECHNOLOGY   (China)

Author keywords

Low Power; Mapping; NoC; Thermal

Indexed keywords

ELECTRIC NETWORK TOPOLOGY; GENETIC ALGORITHMS; INTERNET PROTOCOLS; MULTIOBJECTIVE OPTIMIZATION; NETWORK ARCHITECTURE; PARETO PRINCIPLE; SOLUTIONS;

ASIA-PACIFIC; EFFICIENT SOLUTIONS; HIGHLY EFFICIENT; IP CORES; LOW POWER; MAPPING; MAPPING PROBLEMS; MULTI OBJECTIVES; MULTI-OBJECTIVE GENETIC ALGORITHM; MULTI-OBJECTIVE MAPPING; NETWORK-ON-CHIP; NOC; NOC ARCHITECTURES; NOVEL REPRESENTATION; OBJECTIVE OPTIMIZATION; PARETO-OPTIMAL; PARETO-OPTIMAL SOLUTIONS; PERFORMANCE REQUIREMENTS; THERMAL;

CONFORMAL MAPPING;

EID: 50249127218     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/APCCAS.2006.342418     Document Type: Conference Paper

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