Pseudo-two-dimensional model for double-gate tunnel FETs considering the junctions depletion regions

IEEE Transactions on Electron Devices

Volumn 57, Issue 4, 2010, Pages 827-834

  Bardon, Marie Garcia ^a,b   Neves, Herc P ^a   Puers, Robert ^b   Van Hoof, Chris ^a  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

Analytical modeling; Band to band tunneling; Gated p type intrinsic n type diode; Poisson's equation; Tunnel field effect transistor

Indexed keywords

ANALYTICAL MODELING; BAND TO BAND TUNNELING; GATED P-TYPE-INTRINSIC-N-TYPE DIODE; P-TYPE; POISSON'S EQUATION;

ELECTRIC FIELDS; FIELD EFFECT TRANSISTORS; GATES (TRANSISTOR); POISSON EQUATION; SILICON COMPOUNDS; TUNNEL JUNCTIONS; TUNNELING (EXCAVATION); TWO DIMENSIONAL;

WIND TUNNELS;

EID: 77950300237     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2010.2040661     Document Type: Article

References (21)

1. W. Y. Choi, B.-G. Park, J. D. Lee, and T.-J. King Liu, "Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec," IEEE Trans. Electron Devices, vol.28, no.8, pp. 743-745, Aug. 2007.
2. J. Appenzeller, Y.-M. Lin, J. Knoch, and P. Avouris, "Band-to-band tunneling in carbon nanotube field-effect transistors," Phys. Rev. Lett., vol.93, no.19, pp. 196 805-1-196 805-4, Nov. 2004.
3. K. Boucart and A. M. Ionescu, "Double-gate tunnel FET with high- k gate dielectric," IEEE Trans. Electron Devices, vol.54, no.7, pp. 1725-1733, Jul. 2007.
4. M. Schlosser, K. K. Bhuwalka, M. Sauter, T. Zilbauer, T. Sulima, and I. Eisele, "Fringing-induced drain current improvement in the tunnel fieldeffect transistor with high- k gate dielectrics," IEEE Trans. Electron Devices, vol.56, no.1, pp. 100-108, Jan. 2009.
5. K. K. Bhuwalka, J. Schulze, and I. Eisele, "Simulation approach to optimize the electrical parameters of a vertical tunnel FET," IEEE Trans. Electron Devices, vol.52, no.7, pp. 1541-1547, Jul. 2005.
6. E.-H. Toh, G. H. Wang, L. Chan, G. Samudra, and Y.-C. Yeo, "Device physics and guiding principles for the design of double-gate tunneling field effect transistor with silicon-germanium source heterojunction," Appl. Phys. Lett., vol.91, no.24, pp. 243 505-1-243 505-3, Dec. 2007.
7. K. Boucart and A. Ionescu, "A new definition of threshold voltage in tunnel FETs," Solid State Electron., vol.52, no.9, pp. 1318-1323, Sep. 2008.
8. A. S. Verhulst, W. G. Vandenberghe, K. Maex, and G. Groeseneken, "Boosting the on-current of a n-channel nanowire tunnel field-effect transistor by source material optimization," J. Appl. Phys., vol.104, no.6, p. 064 514-1, Sep. 2008.
9. W. Vandenberghe, A. Verhulst, G. Groeseneken, B. Soree, and W. Magnus, "Analytical model for a tunnel field-effect transistor," in Proc. MELECON, 2008, pp. 923-928.
10. C. Shen, S.-L. Ong, C.-H. Heng, G. Samudra, and Y.-C. Yeo, "A variational approach to the two-dimensional nonlinear Poisson's equation for the modeling of tunneling transistors," IEEE Electron Device Lett., vol.29, no.11, pp. 1252-1255, Nov. 2008.
11. J. Knoch, S. Mantl, Y.-M. Lin, Z. Chen, P. Avouris, and J. Appenzeller, "An extended model for carbon nanotube field-effect transistors," in Proc. DRC, 2004, vol.1, pp. 135-136.
12. P.-F. Wang, "Complementary tunneling-FETs (CTFET) in CMOS technology," Ph.D. dissertation, Technische Universitat München, München, Germany, 2003.
13. K. Boucart and A. M. Ionescu, "Length scaling of the double gate tunnel FET with a high- k gate dielectric," Solid State Electron., vol. 51, no. 11/12, pp. 1500-1507, Nov./Dec. 2007.
14. M. Kumar and A. Orouji, "Two-dimensional analytical threshold voltage model of nanoscale fully depleted SOI MOSFET with electrically induced S/D extensions," IEEE Trans. Electron Devices, vol.52, no.7, pp. 1568- 1575, Jul. 2005.
15. B. Iñiguez, T. A. Fjeldly, A. Lázaro, F. Danneville, and M. J. Deen, "Compact-modeling solutions for nanoscale double-gate and gate-allaround MOSFETs," IEEE Trans. Electron Devices, vol.53, no.9, pp. 2128-2142, Sep. 2006.
16. J.-W. Han, C.-J. Kim, and Y.-K. Choi, "Universal potential model in tied and separated double-gate MOSFETs with consideration of symmetric and asymmetric structure," IEEE Trans. Electron Devices, vol.55, no.6, pp. 1472-1479, Jun. 2008.
17. K. Young, "Short-channel effect in fully depleted SOI MOSFETs," IEEE Trans. Electron Devices, vol.36, no.2, pp. 399-402, Feb. 1989.
18. S. Lin and J. Kuo, "Modeling the fringing electric field effect on the threshold voltage of FD SOI nMOS devices with the LDD/sidewall oxide spacer structure," IEEE Trans. Electron Devices, vol.50, no.12, pp. 2559- 2564, Dec. 2003.
19. S. Sze, Physics of Semiconductor Devices. New York: Wiley, 1981.
20. E. O. Kane, "Zener tunneling in semiconductors," J. Phys. Chem. Solids, vol.12, no.2, pp. 181-188, Jan. 1960.
21. K. Bhuwalka, J. Schulze, and I. Eisele, "Scaling issues of n-channel vertical tunnel FET with ?p+ SiGe layer," in Proc. DRC, 2004, vol.1, pp. 215-216.