Two-dimensional analytical threshold voltage model of nanoscale fully depleted SOI MOSFET with electrically induced S/D extensions

IEEE Transactions on Electron Devices

Volumn 52, Issue 7, 2005, Pages 1568-1575

  Kumar, Mamidala Jagadesh ^a   Orouji, Ali A ^b  

^a INDIAN INSTITUTE OF TECHNOLOGY DELHI   (India)

^b SEMNAN UNIVERSITY   (Iran)

Author keywords

Device scaling; Insulated gate field effect transistor (FET); Short channel effects (SCEs); Silicon on insulator (SOI) MOSFET; Threshold voltage; Two dimensional (2 D) modeling

Indexed keywords

BOUNDARY CONDITIONS; COMPUTER SIMULATION; DIFFERENTIAL EQUATIONS; GATES (TRANSISTOR); MATHEMATICAL MODELS; POISSON EQUATION; SEMICONDUCTOR DOPING; SEMICONDUCTOR JUNCTIONS; SILICON ON INSULATOR TECHNOLOGY; THIN FILMS; THRESHOLD VOLTAGE;

DEVICE SCALING; INSULATED GATE FIELD EFFECT TRANSISTOR; SHORT CHANNEL EFFECTS (SCES); TWO DIMENSIONAL MODELING;

MOSFET DEVICES;

EID: 23944447436     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2005.850624     Document Type: Article

References (20)

1. R. H. Dennard, F. H. Gaensslen, H.-N. Yu, V. L. Rideout, E. Bassous, and A. R. Leblanc, "Design of ion-implanted MOSFETs with very small physical dimensions," IEEE J. Solid-State Circuits, vol. SC-9, no. 5, pp. 256-268, May 1974.
2. A. Chaudhry and M. J. Kumar, "Controlling short-channel effect in deep-submicron SOI MOSFETs for improved reliability: A review," IEEE Trans. Device Mater. Reliabil., vol. 4, no. 3, pp. 99-109, Mar. 2004.
3. G. V. Reddy and M. J. Kumar, "A new dual-material double-gate (DMDG) nanoscale SOI MOSFET - Two-dimensional analytical modeling and simulation," IEEE Trans. Nanotechnol., vol. 4, no. 3, pp. 260-268, Mar. 2005.
4. T. Ghani, K. Mistry, P. Packan, S. Thompson, M. Stettler, S. Tyagi, and M. Bohr, "Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors," in Symp. VLSI Tech. Dig., Jun. 2000, pp. 174-175.
5. X. Tang, V. K. De, and J. D. Meindl, "Intrinsic MOSFET parameter fluctuations due to random dopant placement," IEEE Trans. Very Large Scale (VLSI) Syst., vol. 5, no. 12, pp. 369-376, Dec. 1997.
6. H. Kawaura, T. Sakamoto, T. Baba, Y. Ochiai, J. Fujita, S. Matsui, and J. Sone, "Transistor operation of 30 nm gate-length EJ-MOSFETs," IEEE Electron Device Lett., vol. 19, no. 3, pp. 74-76, Mar. 1998.
7. S. Han, S. Chang, J. Lee, and H. Shin, "50 nm MOSFET with electrically induced source/drain (S/D) extensions," IEEE Trans. Electron Devices, vol. 48, no. 9, pp. 2058-2064, Sep. 2001.
8. H. Noda, F. Murai, and S. Kimura, "Threshold voltage controlled 0.1-μ m MOSFET utilizing inversion layer as extreme shallow source/ drain," in IEDM Tech. Dig., 1993, pp. 123-126.
9. W. Xusheng, Z. Shendong, M. Chan, and P. Chan, "Design of Sub-50 nm ultrathin-body (UTB) SOI MOSFETs with raised S/D," in IEEE Conf. Electron Devices Solid-State Circuits, 2003, pp. 251-254.
10. A. Hartstein, N. F. Albert, A. A. Bright, S. B. Kaplan, B. Robinson, and J. A. Tornello, "A metal-oxide-semiconductor field effect transistor with a 20 nm channel length," J. Appl. Phys., vol. 68, pp. 2493-2495, 1990.
11. H. S. Wong, "Experimental verification of the mechanism of hot-carrier-induced photon emission in N-MOSFETs with a CCD gate structure," in IEDM Tech. Dig., 1991, pp. 549-552.
12. P. S. T. Chang, Y. Kohyama, M. Kakuma, A. Sudo, Y. Asao, J. Kumagai, F. Matsuoka, H. Ishiuchi, and S. Sawada, "High performance deep submicron buried channel PMOSFET using P+ poly-Si spacer induced self-aligned ultra shallow junctions," in IEDM Tech. Dig., 1992, pp. 905-908.
13. Technology Modeling Associates. Palo Alto, CA: MEDICI 4.0, 1997.
14. Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices. Cambridge, U.K.: Cambridge Univ. Press, 1998.
15. K. K. Young, "Short-channel effect in fully depleted SOI-MOSFETs," IEEE Trans. Electron Devices, vol. 47, no. 1, pp. 113-120, Jan. 2000.
16. H.O. Joachim, Y. Yamaguchi, K. Ishikawa, Y. Inoue, and T. Nishimura, "Simulation and two-dimensional analytical modeling of subthreshold slope in ultrathin-film soi MOSFETs down to 0.1μm gate length,"IEEE Trans. Electron Devices, vol. 40, no. 10, pp. 1812-1817, Oct. 1993.
17. S. R. Banna, P. C. H. Chan, P. K. Ko, C. T. Nguyen, and M. Chan, "Threshold voltage model for deep-submicrometer fully depleted SOI MOSFETs," IEEE Trans. Electron Devices, vol. 42, no. 11, pp. 1949-1955, Nov. 1995.
18. K. Suzuki and S. Pidin, "Short-channel single-gate SOI MOSFET model," IEEE Trans. Electron Devices, vol. 50, no. 5, pp. 1297-1305, May 2003.
19. K. S. Kalonia and F. C. Jain, "A two-dimensional analytical model for MOSFETs operating at 77 K," in Proc. IEEE 8th Biennial University/Government/Industry Microelectronics Symp., 1989, pp. 182-187.
20. M.J. Kumar and A. Chaudhry, "Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs," IEEE Trans. Electron Devices, vol. 51, no. 4, pp. 569-574, Apr. 2004.