Statistical leakage estimation based on sequential addition of cell leakage currents

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 18, Issue 4, 2010, Pages 602-615

  Kim, Wook ^a   Do, Kyung Tae ^b   Kim, Young Hwan ^a  

^a Pohang University of Science and Technology (POSTECH)   (South Korea)

^b SAMSUNG Electronics   (South Korea)

Author keywords

Leakage current; Process variation; Statistical leakage estimation; Yield estimation

Indexed keywords

ACCURATE ANALYSIS; CELL LEAKAGE CURRENTS; LEAKAGE ESTIMATION; MC SIMULATION; MONTE CARLO SIMULATIONS; NOVEL METHODS; PROCESS VARIATION; SEQUENTIAL ADDITION; STANDARD DEVIATION; STATE DEPENDENCE; VIRTUAL CELLS; WILKINSON; YIELD ESTIMATION;

CHANNEL CAPACITY; ESTIMATION; THRESHOLD VOLTAGE;

LEAKAGE CURRENTS;

EID: 77950298754     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2009.2013956     Document Type: Article

References (34)

1. S. Narendra, V. De, S. Borkar, D. Antoniadis, and A. Chandrakasan, "Full-chip sub-threshold leakage power prediction model for sub-0.18 μm CMOS," in Proc. Int. Symp. Low Power Electron. Des., 2002, pp. 19-23.
2. A. Srivastava, R. Bai, D. Blaauw, and D. Sylvester, "Modeling and analysis of leakage power considering within-die process variations," in Proc. Int. Symp. Low Power Electron. Des., 2002, pp. 64-67.
3. S. Mukhopadhyay and K. Roy, "Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variation," in Proc. Int. Symp. Low Power Electron. Des., 2003, pp. 172-175.
4. R. Rao, A. Srivastava, D. Blaauw, and D. Sylvester, "Statistical estimation of leakage current considering inter-and intra-die process variation," in Proc. Int. Symp. Low Power Electron. Des., 2003, pp. 84-89.
5. R. Rao, A. Devgan, D. Blaauw, and D. Sylvester, "Parametric yield estimation considering leakage variability," in Proc. Des. Autom. Conf., 2004, pp. 442-447.
6. H. Chang and S. S. Sapatnekar, "Full-chip analysis of leakage power under process variations, including spatial correlations," in Proc. Des. Autom. Conf., 2005, pp. 523-528.
7. C. Visweswariah, K. Ravindran, K. Kalafala, S. G. Walker, S. Narayan, D. K. Beece, J. Piaget, N. Venkateswaran, and J. G. Hemmett, "First-order incremental block-based statistical timing analysis," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol.25, no.10, pp. 2170-2180, Oct. 2006.
8. N. C. Beaulieu, A. A. Abu-Dayya, and P. J. McLane, "Comparison of methods of computing lognormal sum distributions and outages for digital wireless applications," in Proc. IEEE Int. Conf. Commun., 1994, pp. 1270-1275.
9. Y. Cao, T. Sato, M. Orshansky, D. Sylvester, and C. Hu, "New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation," in Proc. IEEE Custom Integr. Circuits Conf., 2000, pp. 201-204.
10. R. M. Rao, R. B. Brown, K. Nowka, and J. L. Burns, "Analysis and mitigation of CMOS gate leakage," in Proc. Austin Center Advanced Studies Conf., 2004, pp. 7-11.
11. K. A. Bowman, L. Wang, X. Tang, and J. D. Meindl, "A circuit-level perspective of the optimum gate oxide thickness," IEEE Trans. Electron Devices, vol.48, no.8, pp. 1800-1810, Aug. 2001.
12. N. Marlow, "A normal limit theorem for power sums of independent random variables," Bell Syst. Tech. J., vol.46, pp. 2081-2090, 1967.
13. R. V. Hogg, J. W. McKean, and A. T. Craig, Introduction to Mathematical Statistics. Englewood Cliffs, NJ: Prentice-Hall, 2005.
14. S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, and V. De, "Parameter variations and impact on circuits and microarchitecture," in Proc. Des. Autom. Conf., 2003, pp. 338-342.
15. S. R. Nassif, "Design for variability in DSM technologies," in Int. Symp. Quality Electron. Des., 2000, pp. 451-454.
16. B. Doyle, R. Arghavani, D. Barlage, S. Datta, M. Doczy, J. Kavalieros, A. Murthy, and R. Chau, "Transistor elements for 30 nm physical gate lengths and beyond," Intel Technol. J., vol.6, no.2, pp. 42-54, May 2002.
17. W. Liu, X. Jin, X. Xi, J. Chen, M. C. Jeng, Z. Liu, Y. Cheng, K. Chen, M. Chan, K. Hui, J. Huang, R. Tu, P.K. Ko, and C. Hu, "BSIM3v3.3 MOSFET Model Users Manual," Jul. 2005. [Online]. Available: http:// www-device.eecs.berkeley.edu/∼bsim3/get.html
18. M. V. Dunga et al., "BSIM4.6.1 MOSFET Model Users Manual," May 2007. [Online]. Available: http://www-device.eecs.berkeley.edu/∼bsim3/bsim4- get.html
19. E. Acar, A. Devgan, R. Rao, Y. Liu, H. Su, S. Nassif, and J. Burns, "Leakage and leakage sensitivity computation for combinational circuits," in Proc. Int. Symp. Low Power Electron. Des., 2003, pp. 96-99.
20. N. H. E. Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective. Reading, MA: Addison-Wesley, 2005.
21. K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, "Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOScircuits," Proc. IEEE, vol.91, no.2, pp. 305-327, Feb. 2003.
22. C.Visweswariah, "Death, taxes and failing chips," in Proc. Des. Autom. Conf., 2003, pp. 343-347.
23. A. Agarwal, D. Blaauw, V. Zolotov, S. Sundareswaran, M. Zhao, K. Gala, and R. Panda, "Statistical delay computation considering spatial correlations," in Proc. Asia South Pacific Des. Autom. Conf., 2003, pp. 271-276.
24. A. Srivastava, S. Shah, K. Agarwal, D. Sylvester, D. Blaauw, and S. Director, "Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance," in Proc. Des. Autom. Conf., 2005, pp. 535-540.
25. D. J. Hyun, K. T. Do, and Y. H. Kim, "Monte-Carlo simulation with convergences of mean and variance for a SoC design," in Int. Tech. Conf. Circuits/Syst., Comput. Commun., 2007, vol.3, pp. 1205-1206.
26. L. Zhang, W. Chen, Y. Hu, J. A. Gubner, and C.C.-P. Chen, "Correlation-preserved statistical timing with a quadratic form of Gaussian variables," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol.25, no.11, pp. 2437-2449, Nov. 2006.
27. H. Chang and S. S. Sapatnekar, "Prediction of leakage power under process uncertainties," ACM Trans. Des. Autom. Electron. Syst., vol.12, no.2, pp. 1-27, Apr. 2007.
28. F. Brgles, D. Bryan, and K. Kozminski, "Combinational profiles of sequential benchmark circuits," in Proc. Int. Symp. Circuits Syst., 1989, pp. 1929-1934.
29. M. Keating, D. Flynn, R. Aitken, A. Gibbons, and K. Shi, Low Power Methodology Manual for System-on-Chip Design. New York: Springer-Verlag, 2007.
30. A. Agarwal, S. Mukhopadhyay, A. Raychowdhury, K. Roy, and C. H. Kim, "Leakage power analysis and reduction for nanoscale circuits," IEEE Micro, vol.26, no.2, pp. 68-80, Mar./Apr. 2006.
31. T. Lim and Y. Kim, "Effect of band-to-band tunneling leakage on 28 nm MOSFET design," Electron. Lett., vol.44, no.2, pp. 157-158, Jan. 2008.
32. J. Xiong, V. Zolotov, and L. He, "Robust extraction of spatial correlation," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol.26, no.4, pp. 619-631, Apr. 2007.
33. M. H. Abu-Rahma and M. Anis, "Variability in VLSI circuits: Sources and design considerations," in Proc. Int. Symp. Circuits Syst., 2007, pp. 3215-3218.
34. F. Liu, "A general framework for spatial correlation modeling in VLSI design," in Proc. Des. Autom. Conf., 2007, pp. 817-822.