Leakage power analysis and reduction for nanoscale circuits

IEEE Micro

Volumn 26, Issue 2, 2006, Pages 68-80

  Agarwal, Amit ^a   Mukhopadhyay, Saibal ^b   Raychowdhury, Arijit ^b   Roy, Kaushik ^b   Kim, Chris H ^c  

^a INTEL CORPORATION   (United States)

^b PURDUE UNIVERSITY   (United States)

^c UNIVERSITY OF MINNESOTA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; LEAKAGE CURRENTS; NANOSTRUCTURED MATERIALS; RANDOM ACCESS STORAGE; SEMICONDUCTOR DOPING; THRESHOLD VOLTAGE; TRANSISTORS;

GATE OXIDE; LEAKAGE POWER ANALYSIS; POWER DISSIPATION;

CMOS INTEGRATED CIRCUITS;

EID: 33646013886     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2006.39     Document Type: Article

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