Random fluctuations in scaled MOS devices

International Conference on Simulation of Semiconductor Processes and Devices, SISPAD

Volumn , Issue , 2009, Pages

  Takeuchi, Kiyoshi ^a,b   Nishida, Akio ^b   Hiramoto, Toshiro ^b,c  

^a RENESAS TECHNOLOGY CORP   (Japan)

^b SEMICONDUCTOR LEADING EDGE TECHNOLOGIES INC   (Japan)

^c UNIVERSITY OF TOKYO   (Japan)

Author keywords

Large scale integrated circuit; MOSFET; Random dopant fluctuation; Variability; Variation

Indexed keywords

ATOMIC SCALE; LARGE SCALE INTEGRATED CIRCUIT; MOS TRANSISTORS; MOS-FET; RANDOM DOPANT FLUCTUATION; RANDOM FLUCTUATION; RESEARCH RESULTS;

INTEGRATED CIRCUITS; MOSFET DEVICES; THRESHOLD VOLTAGE; TRANSISTOR TRANSISTOR LOGIC CIRCUITS;

MOS DEVICES;

EID: 74349093409     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SISPAD.2009.5290243     Document Type: Conference Paper

References (28)

1. G. Declerck, "Look into the future of nanoelectronics", 2005 Symp. VLSI Tech., pp.6-10.
2. K. Kuhn, C. Kenyon, A. Kornfeld, M. Liu, A. Maheshwari, W. Shih, S. Sivakumar, G. Taylor, P. VanDerVoorn, and K. Zawadzki, "Managing process variation in Intel's 45nm CMOS technology," Intel Technology Journal, 12, pp.93-109, 2008.
3. K. Takeuchi, T. Fukai, T. Tsunomura, A. T. Putra, A. Nishida, S. Kamohara, and T. Hiramoto, "Understanding random threshold voltage fluctuation by comparing multiple fabs and technologies," 2007 Int. Electron Devices Meeting, pp.467-470.
4. S. K. Springer, S. Lee, N. Lu, E. J. Nowak, J. Plouchart, J. S. Watts, R. Q. Williams, and N. Zamdmer, "Modeling of variation in submicrometer CMOS ULSI technologies," IEEE Trans. Electron Devices, 53, pp.2168-2178, 2006.
5. L. Capodieci, "From optical proximity correction to lithography-driven enhancement technology and the roadmap enablers for the next decade," Proc. SPIE, 6154, 615401, 2006.
6. C. W. Liu, S. Maikap, and C.-Y. Yu, "Mobility enhancement technologies," IEEE Circuits & Devices Magazine, 21, pp.21-36, 2005.
7. M. C. Choi and L. Milor, "Impact on circuit performance of deterministic within-die variation in nanoscale semiconductor manufacturing," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, 25, pp.1350-1367, 2006.
8. K. R. Lakshmikumar, R. A. Hadaway, and M. A. Copeland, "Characterization and modeling of mismatch in MOS transistors for precision analog design," IEEE J. Solid-State Circuits, SC-21, pp.1057-1066, 1986.
9. T. Tsunomura, A. Nishida, F. Yano, A. T. Putra, K. Takeuchi, S. Inaba, S. Kamohara, K. Terada, T. Hiramoto, and T. Mogami, "Analyses of 5σ Vth fluctuation in 65nm-MOSFETs using Takeuchi plot," 2008 Symp. VLSI Tech., pp.156-157.
10. R. W. Keyes, "The effect of randomness in the distribution of impurity atoms on FET thresholds," Appl. Phys., 8, pp.251-259, 1975.
11. A. Asenov, S. Kaya, and J. H. Davis, "Threshold voltage fluctuations in decanano MOSFETs due to local oxide thickness variations," IEEE Trans. Electron Devices, 49, pp.112-119, 2002.
12. H.-W. Kim, J.-Y. Lee, J. Shin, S.-G. Woo, H.-K. Cho, and J.-T. Moon, "Experimental investigation of the impact of LWR on sub-100-nm device performance," IEEE Trans. Electron Devices, 51, pp.1984-1988, 2004.
13. A. R. Brown, G. Roy, and A. Asenov, "Poly-Si-gate-related variability in decananometer MOSFETs with conventional architecture," IEEE Trans. Electron Devices, 54, pp.3056-3063, 2007.
14. H. Fukutome, Y. Momiyama, T. Kubo, Y. Tagawa, T. Aoyama, and H. Arimoto, "Direct evaluation of gate line edge roughness impact on extension profiles in sub-50-nm n-MOSFETs," IEEE Trans. Electron Devices, 53, pp.2755-2763, 2006.
15. K. Takeuchi, A. Nishida, and T. Hiramoto, "Normalization of random threshold voltage fluctuation for fair comparison between technologies, process conditions and device designs," 2007 Silicon Nanoelectronics Workshop, pp.7-8.
16. S. Takagi, A. Toriumi, M. Iwase, and H. Tango, "On the universality of inversion layer mobility in Si MOSFET's: part I - effects of substrate impurity concentration," IEEE Trans. Electron Devices, 41, pp.2357-2362, 1994.
17. M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS transistors," IEEE J. Solid-State Circuits, 24, pp.1433-1439, 1989.
18. K. Takeuchi, T. Tatsumi, and A. Furukawa, "Channel engineering for the reduction of random-dopant-placement-induced threshold voltage fluctuation," 1997 Int. Electron Devices Meeting, pp.841-844.
19. A. Asenov, A. Cathignol, B. Cheng, K. P. McKenna, A. R. Brown, A. L. Shluger, D. Chanemougame, K. Rochereau, and G. Ghibaudo, "Origin of the asymmetry in the magnitude of the statistical variability of n-and p-channel poly-Si gate bulk MOSFETs," IEEE Electron Device Lett., 29, pp.913-915, 2008.
20. T. Tsunomura, A. Nishida, F. Yano, A. T. Putra, K. Takeuchi, S. Inaba, S. Kamohara, K. Terada, T. Mama, T. Hiramoto, and T. Mogami, "Analysis of extra Vt variability sources in NMOS using Takeuchi plot," to be presented at 2009 Symp. VLSI Tech., 6A-1.
21. G. Tsutsui, K. Tsunoda, N. Kariya, Y. Akiyama, T. Abe, S. Maruyama, T. Fukase, M. Suzuki, Y. Yamagata, and K. Imai, "Reduction of Vth variation by work function optimization for 45-nm node SRAM cell," 2008 Symp. VLSI Tech., pp.158-159.
22. H. S. Yang et al., "Scaling of 32nm low power SRAM with high-k metal gate," 2008 Int. Electron Devices Meeting, pp.233-236.
23. N. Sugii, R. Tsuchiya, T. Ishigaki, Y. Morita, H. Yoshimoto, K. Torii, and S. Kimura, "Comprehensive study on Vth variability in silicon on thin BOX (SOTB) CMOS with small random-dopant fluctuation: finding a way to further reduce variation," 2008 Int. Electron Devices Meeting, pp.249-252.
24. H. Kawasaki et al., "Demonstration of highly scaled FinFET SRAM cells with high-k/metal gate and investigation of characteristic variability for the 32nm node and beyond," 2008 Int. Electron Devices Meeting, pp.237-240.
25. S. D. Suk et al., "Investigation of nanowire size dependency on TSNWFET," 2007 Int. Electron Devices Meeting, pp.891-894.
26. I. Ban, U. E. Avci, D. L. Kencke, and P. L. D. Chang, "A scaled floating body cell (FBC) memory with high-k+metal gate on thin-silicon and thin-BOX for 16-nm technology node and beyond," 2008 Symp. VLSI Tech., pp.92-93.
27. O. Weber et al., "High immunity to threshold voltage variability in undoped ultra-thin FDSOI MOSFETs and its physical understanding," 2008 Int. Electron Devices Meeting, pp.245-248.
28. K. Takeuchi, T. Nagumo, S. Yokogawa, K. Imai, and Y. Hayashi, "Single-charge-based modeling of transistor characteristics fluctuations based on statistical measurement of RTN amplitude," to be presented at 2009 Symp. VLSI Tech., 3B-5.