Multilevel interconnect with air-gap structure for next-generation interconnections

IEEE Transactions on Electron Devices

Volumn 56, Issue 11, 2009, Pages 2675-2682

  Noguchi, Junji ^a   Oshima, Takayuki ^b   Matsumoto, Takashi ^b   Uno, Shoichi ^b   Sato, Kiyohiko ^b  

^a Strategy Planning and Development Office   (Japan)

^b HITACHI LTD   (Japan)

Author keywords

Air gap; Capacitance; Copper; Dielectric breakdown; Electromigration (EM); Integrated circuit interconnection; Integrated circuit reliability

Indexed keywords

AIR GAP; AIR-GAPS; BASE STRUCTURE; CAPACITANCE REDUCTION; DIELECTRIC BREAKDOWN; EFFECTIVE DIELECTRIC CONSTANTS; GAP FORMATION; GENERATION INTERCONNECTION; INTEGRATED-CIRCUIT INTERCONNECTION; INTEGRATED-CIRCUIT RELIABILITY; INTER-LAYER DIELECTRICS; ORDERS OF MAGNITUDE; RING OSCILLATOR; SELF-ALIGNED; SIMULATION RESULT; STRESS-INDUCED VOIDING; TDDB LIFETIME; TIME-DEPENDENT DIELECTRIC BREAKDOWN;

CAPACITANCE; ELECTROMIGRATION; OPTICAL INTERCONNECTS; OSCILLATORS (ELECTRONIC); RELIABILITY; SOLID-STATE SENSORS; TEMPERATURE CONTROL;

ELECTRIC BREAKDOWN;

EID: 70350710012     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2009.2030538     Document Type: Article

References (23)

1. T. Nakamura and A. Nakashima, "Robust multilevel interconnects with a nano-clustering porous low-k (k < 2.3)," in Proc. IITC 2004, pp. 175-177.
2. N. Matsunaga, N. Nakamura, K. Higashi, H. Yamaguchi, T. Watanabe, K. Akiyama, S. Nakao, K. Fujita, H. Miyajima, S. Omoto, A. Sakata, T. Katata, Y. Kagawa, H. Kawashima, Y. Enomoto, T. Hasegawa, and H. Shibata, "BEOL process integration technology for 45 nm node porous low-k/copper interconnects," in Proc. IITC, 2005, pp. 6-8.
3. T. Jacobs, K. Brennan, R. Carpio, K. Mosig, J.-C. Lin, H. Cox, W. Mlynko, J. Fourcher, J. Bennett, J. Wolf, R. Augur, and P. Gillespie, "Voiding in ultra porous low-k materials proposed mechanism, detection and possible solutions," in Proc. IITC, 2002, pp. 236-238.
4. K. Fujita, H. Miyajima, R. Nakata, and N. Miyashita, "Notable improvement in porous low-k film properties using electron-beam cure method," in Proc. IITC, 2003, pp. 106-108.
5. J. Noguchi, T. Saito, N. Ohashi, H. Ashihara, H. Maruyama, M. Kubo, H. Yamaguchi, D. Ryuzaki, K. Takeda, and K. Hinode, "Impact of low-k dielectrics and barrier metals on TDDB lifetime of Cu interconnects," in Proc. IRPS, 2001, pp. 355-359.
6. E. T. Ogawa, J. Kim, G. S. Haase, H. C. Mogul, and J. W. McPherson, "Leakage, breakdown, and TDDB characteristics of porous low-k silica-based interconnect dielectrics," in Proc. IRPS, 2003, pp. 166-172.
7. T. Mourier, V. Jousseaume, F. Fusalba, C. Lecornec, P. Maury, G. Passemard, P. Haumesser, S. Maitrejean, M. Cordeau, R. Pantel, F. Pierre, M. Fayolle, and H. Feldis, "Porous low k pore sealing process study for 65 nm and below technologies," in Proc. IITC, 2003, pp. 245-247.
8. B. P. Shieh, L. C. Bassman, D. K. Kim, K. C. Saraswat, M. D. Deal, and J. P. McVittie, "Integration and reliability issues for low capacitance airgap interconnect studies," in Proc. IITC, 1998, pp. 125-127.
9. O. Demolliens, Y. Morand, M. Fayolle, M. Cochet, M. Assous, H. Feldis, D. Louis, J. C. Royer, Y. Gobil, G. Passemard, P. Maury, F. Jourdan, M. Cordeau, T. Morel, L. Perroud, L. Ulmer, J. F. Lugand, and D. Renaud, "Copper-SiOC-AirGap integration in a double level metal interconnect," in Proc. IITC, 2000, pp. 276-277.
10. 2 air gap interconnect for sub 0.1 micron CMOS technologies," in Proc. IITC 2001, pp. 298-300.
11. L. G. Gosset, V. Arnal, P. Brun, M. Broekaart, C. Monget, N. Casanova, M. Rivoire, J. C. Oberlin, and J. Torres, "Integration of SiOC air gaps in copper interconnects," Microelectron. Eng., vol. 70, no. 2-4, pp. 274-279, Nov. 2003.
12. M. B. Anand, M. Yamada, and H. Shibata, "NURA: A feasible gas-dielectric interconnect process," in VLSI Symp. Tech. Dig., 1996, pp. 82-83.
13. L. G. Gosset, F. Gaillard, D. Bouchu, R. Gras, J. de Pontcharra, S. Orain, O. Cueto, P. Lyan, O. Louveau, G. Passemard, and J. Torres, "Multi-level Cu interconnects integration and characterization with air gap as ultralow k material formed using a hybrid sacrificial oxide/polymer stack," in Proc. IITC, 2007, pp. 58-60.
14. T. Harada, A. Ueki, K. Tomita, K. Hashimoto, J. Shibata, H. Okamura, K. Yoshikawa, T. Iseki, M. Higashi, S. Maejima, K. Nomura, K. Goto, T. Shono, S. Muranaka, N. Torazawa, S. Hirao, M. Matsumoto, T. Sasaki, S. Matsumoto, S. Ogawa, M. Fujisawa, A. Ishii, M. Matsuura, and T. Ueda, "Extremely low Keff (∼1.9) Cu interconnects with air gap formed using SiOC," in Proc. IITC, 2007, pp. 141-143.
15. S. Nitta, D. Edelstein, S. Ponoth, L. Clevenger, X. Liu, and T. Standaert, "Performance and reliability of airgaps for advanced BEOL interconnects," in Proc. IITC, 2008, pp. 191-192.
16. N. Nakamura, N. Matsunaga, T. Kaminatsui, K. Watanabe, and H. Shibata, "Cost-effective air-gap interconnects by all-in-one post-removing process," in Proc. IITC, 2008, pp. 193-195.
17. J. Noguchi, T. Fujiwara, K. Sato, T. Nakamura, M. Kubo, S. Uno, K. Ishikawa, T. Saito, N. Konishi, Y. Yamada, and T. Tamaru, "Simple self-aligned air-gap interconnect process with Cu/FSG structure," in Proc. IITC, 2003, pp. 68-70.
18. J. Noguchi, K. Sato, N. Konishi, S. Uno, T. Oshima, U. Tanaka, K. Ishikawa, H. Ashihara, T. Saito, M. Kubo, H. Aoki, and T. Fujiwara, "Reliability of air-gap Cu interconnect and approach to selective W sealing using 90 nm node technology," in Proc. IITC, 2004, pp. 81-83.
19. S. Uno, J. Noguchi, H. Ashihara, T. Oshima, K. Sato, N. Konishi, T. Saito, and K. Hara, "Dual damascene process for air-gap Cu interconnects using conventional CVD films as sacrificial layers," in Proc. IITC, 2005, pp. 174-176.
20. J. Noguchi, T. Oshima, T. Matsumoto, S. Uno, K. Sato, N. Konishi, T. Saito, M. Miyauchi, S. Hotta, H. Aoki, T. Kikuchi, K. Watanabe, and K. Kikushima, "Misalignment-free air-gap (MFAG) interconnect with via base structure for 45/65 nm node and below," in Proc. IITC, 2006, pp. 167-169.
21. J. Noguchi, N. Ohashi, J. Yasuda, T. Jimbo, H. Yamaguchi, N. Owada, K. Takeda, and K. Hinode, "TDDB improvement in Cu metallization under bias stress," in Proc. IRPS, 2000, pp. 339-343.
22. 3-plasma treatment and CMP modification on TDDB improvement in Cu metallization," IEEE Trans. Electron Devices, vol. 48, no. 7, pp. 1340-1345, Jul. 2001.
23. ITRS (International Technology Roadmap for Semiconductors). [Online]. Available: http://public.itrs.net/