-
2
-
-
84961922490
-
Integration and reliability issues for low capacitance air-gap interconnect structures
-
Shieh B., Bassman L., Kim D., Saraswat K., Diel M., McVittie J. Integration and reliability issues for low capacitance air-gap interconnect structures. International Interconnect Technology Conference:1998;125-127.
-
(1998)
International Interconnect Technology Conference
, pp. 125-127
-
-
Shieh, B.1
Bassman, L.2
Kim, D.3
Saraswat, K.4
Diel, M.5
McVittie, J.6
-
3
-
-
0033342410
-
A multilevel interconnect technology with intrametal air gap for high performance 0.25 μm and beyond devices manufacturing
-
Lin M., Chang C.Y., Huang T.Y., Lin M.L. A multilevel interconnect technology with intrametal air gap for high performance 0.25 μm and beyond devices manufacturing. Japanese J. Appl. Phys. 38:(11):1999;6240-6246.
-
(1999)
Japanese J. Appl. Phys.
, vol.38
, Issue.11
, pp. 6240-6246
-
-
Lin, M.1
Chang, C.Y.2
Huang, T.Y.3
Lin, M.L.4
-
5
-
-
15044363369
-
Integration of a 3 level Cu-SiO2 air gap interconnect for sub 0.1 micron CMOS technologies
-
Arnal V., Torres J., Gayet Ph., Gonella R., Spinelli Ph., Guillermet M., Vérove Ch. Integration of a 3 level Cu-SiO2 air gap interconnect for sub 0.1 micron CMOS technologies. International Interconnect Technology Conference:2001;143.
-
(2001)
International Interconnect Technology Conference
, pp. 143
-
-
Arnal, V.1
Torres, J.2
Gayet, Ph.3
Gonella, R.4
Spinelli, Ph.5
Guillermet, M.6
Vérove, Ch.7
-
6
-
-
0036133214
-
Optimization of CVD dielectric process to achieve reliable ultra low-k air gaps
-
Arnal V., Torres J., Reynard J.-Ph., Gaillet Ph., Vérove Ch., Guillermet M., Spinelli Ph. Optimization of CVD dielectric process to achieve reliable ultra low-k air gaps. Microelectron. Eng. 60:2002;143-148.
-
(2002)
Microelectron. Eng.
, vol.60
, pp. 143-148
-
-
Arnal, V.1
Torres, J.2
Reynard, J.-Ph.3
Gaillet, Ph.4
Vérove, Ch.5
Guillermet, M.6
Spinelli, Ph.7
-
7
-
-
0033280030
-
Integration of 3 level air gap interconnect for sub-quarter micron CMOS
-
T. Ueda, K. Yamashita, E. Tamaoka, H. Sato, K. Egashira, N. Aoi, M. Ogura, Integration of 3 level air gap interconnect for sub-quarter micron CMOS, Proc. of the 1999 VLSI symposium, VLSI Technical Digest (1999) 111.
-
(1999)
Proc. of the 1999 VLSI Symposium, VLSI Technical Digest
, pp. 111
-
-
Ueda, T.1
Yamashita, K.2
Tamaoka, E.3
Sato, H.4
Egashira, K.5
Aoi, N.6
Ogura, M.7
-
8
-
-
4243308884
-
Fabrication of air-gaps between Cu interconnects for low intralevel K
-
M. Bhusari, D. Wedlake, A. Kohl, C. Case, P. Klemens, J. Miner, B. Chan Lee, J. Gutmann, J. Lee, R. Shick, L. Rhodes, Fabrication of air-gaps between Cu interconnects for low intralevel K, in: MRS Symposium Proceedings, 612 (2000) D4.8.1-D4.8.6.
-
(2000)
MRS Symposium Proceedings
, vol.612
-
-
Bhusari, M.1
Wedlake, D.2
Kohl, A.3
Case, C.4
Klemens, P.5
Miner, J.6
Chan Lee, B.7
Gutmann, J.8
Lee, J.9
Shick, R.10
Rhodes, L.11
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