Alleviating thermal constraints while maintaining performance via silicon- based on-chip optical interconnects

Unique Chips and Systems

Volumn , Issue , 2007, Pages 339-356

  Nelson, Nicholas ^a   Briggs, Gregory ^a   Haurylau, Mikhail ^a   Chen, Guoqing ^a   Chen, Hui ^a   Friedman, Eby G ^a   Fauchet, Philippe M ^a   Albonesi, David H ^b  

^a UNIVERSITY OF ROCHESTER   (United States)

^b Cornell University ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 70350458524     PISSN: None     EISSN: None     Source Type: Book    
DOI: None     Document Type: Chapter

References (37)

1. Arctic Silver Incorporated. The Arctic Silver 5 Specifications. http://www.arcticsilver.com/as5.htm, 2004.
2. C. A. Barrios, V. R. D. Almeida, and M. Lipson. Electrooptic modulation of silicon-on-insulator submicrometer-size waveguide devices. Journal of Lightwave Technology, 21(10):2332, Oct. 2003.
3. C. A. Barrios, V. R. d. Almeida, and M. Lipson. Compact silicon tunable Fabry-Perot resonator with low power consumption. IEEE Photonics Technology Letters, 16(2):506, Feb. 2004.
4. D. Brooks, M. Martonosi, and V. Tiwari. Wattch: A framework for architecturallevel power analysis and optimizations. In Proceedings of the 27th Annual International Symposium on Computer Architecture, pages 83-94, June 2000.
5. D. Burger and T. Austin. The simplescalar toolset, version 2.0. Technical Report TR-97-1342, University of Wisconsin-Madison, June 1997.
6. R. T. Chang, N. Talwalkar, C. P. Yue, and S. S. Wong. Near speed-of-light signaling over on-chip electrical interconnects. IEEE Journal of Solid-State Circuits, 38(5):834-838, May 2003.
7. G. Chen, H. Chen, M. Haurylau, N.A. Nelson, D. H. Albonesi, P. M. Fauchet, and E. G. Friedman, “Predictions of CMOS Compatible On-Chip Optical Interconnect,” Integration, the VLSI Journal, Volume 40, Issue 4, pp. 434-446, July 2007.
8. G. Chen, H. Chen, M. Haurylau, N. Nelson, D. H. Albonesi, P. M. Fauchet, and E. G. Friedman. Electrical and optical on-chip interconnects in future microprocessors. In IEEE International Symposium on Circuits and Systems, May 2005.
9. G. Chen, H. Chen, M. Haurylau, N. Nelson, P. M. Fauchet, E. G. Friedman, and D. H. Albonesi. Predictions of CMOS compatible on-chip optical interconnect. In Proceedings of the IEEE/ACM International Workshop on System Level Interconnect Prediction, Apr. 2005.
10. Y.-K. Cheng and S.-M. Kang. A temperature-aware simulation environment for reliable ULSI chip design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 19(10):1211-1220, Oct. 2000.
11. B. S. Cherkauer and E. G. Friedman. A unified design methodology for CMOS tapered buffers. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 3(1):99-111, Mar. 1995.
12. Z. Chishti, M. D. Powell, and T. N. Vijaykumar. Distance associativity for high-performance energy-efficient non-uniform cache architectures. In Proceedings of the 36th International Symposium on Microarchitecture, pages 55-66, Dec. 2003.
13. J. Donald and M. Martonosi. Temperature-aware design issues for SMT and CMP architectures. In Fifth Workshop on Complexity-Effective Design, 2004 June.
14. A. El-Moursy, R. Garg, S. Dwarkadas, and D. H. Albonesi. Partitioning multithreaded processors with large number of threads. In IEEE International Symposium on Performance Analysis of Systems and Software, Austin, Texas, Mar. 2005.
15. S. Ghiasi and D. Grunwald. Thermal management with asymmetric dual core designs. Technical Report CU-CS-965-03, Department of Computer Science, University of Colorado, 2003.
16. M. Haurylau, G. Chen, H. Chen, J. Zhang, N. A. Nelson, D. H. Albonesi, E. G. Friedman, and P. M. Fauchet, “On-Chip Optical Interconnect Roadmap: Challenges and Critical Directions,” IEEE Journal of Selected Topics in Quantum Electronics, Special Issue on Silicon Photonics, Vol. 12, No. 6, pp. 1699-1705, November/December 2006.
17. M. Huang, J. Renau, S. Yoo, and J. Torrellas. The Design of DEETM: A framework for dynamic energy efficiency and temperature management. Journal of Instruction-Level Parallelism, 3, Oct. 2001.
18. W. Huang, M. R. Stan, K. Skadron, K. Sankaranarayanan, S. Ghosh, and S. Velusamy. Compact thermal modeling for temperature-aware design. In Proceedings of the 41st IEEE/ACM Design Automation Conference, June 2004.
19. R. E. Kessler. The Alpha 21264 microprocessor. IEEE Micro, pages 24-36, Mar./ Apr. 1999.
20. N. S. Kim, T. Austin, D. Blaauw, T. Mudge, K. Flautner, J. S. Hu, M. J. Irwin, M. Kandemir, and V. Narayanan. Leakage current: Moore’s law meets static power. IEEE Computer, 36(12):68-75, Dec. 2003.
21. F. Latorre, J. González, and A. González. Back-end assignment schemes for clustered multithreaded processors. In Proceedings of the 18th Annual ACM International Conference on Supercomputing, pages 316-325, June 2004.
22. S. Lee. How to select a heat sink. Electronics Cooling, 1(1), June 1995.
23. A. Liu, R. Jones, L. Liao, D. Samara-Rubio, D. Rubin, O. Cohen, R. Nicolaescu, and M. Paniccia. A high-speed silicon optical modulator based on a metaloxide-semiconductor capacitor. Nature, 427:615-618, Feb. 2004.
24. R. Lytel, H. L. Davidson, N. Nettleton, and T. Sze. Optical interconnections within modern high-performance computing systems. Proceedings of the IEEE, 88(6):758-763, June 2000.
25. D. A. B. Miller. Rationale and challenges for optical interconnects to electronic chips. Proceedings of the IEEE, 88(6):728-749, June 2000.
26. J. Oh, J. Campbell, S. G. Thomas, S. Bharatan, R. Thoma, C. Jasper, R. E. Jones, and T. E. Zirkle. Interdigitated Ge p-i-n photodetectors fabricated on a Si substrate using graded SiGe buffer layers. IEEE Journal of Quantum Electronics, 38(9):1238-1241, Sept. 2002.
27. M. Rencz, V. Szekely, A. Poppe, and B. Courtois. Friendly tools for the thermal simulation of power packages. International Workshop on Integrated Power Packaging, 2000, pages 51-54.
28. E. Rohou and M. D. Smith. Dynamically managing processor temperature and power. In Proceedings of the 2nd Workshop on Feedback-Directed Optimization, Nov. 1999.
29. S. Sair and M. Charney. Memory behavior of the SPEC2000 benchmark suite. Technical report, IBM T. J. Watson Research Center, Oct. 2000.
30. Semiconductor Industry Association. The International Technology Roadmap for Semiconductors. 2003.
31. K. Skadron, M. R. Stan, K. Sankaranarayanan, W. Huang, S. Velusamy, and D. Tarjan. Temperature-aware microarchitecture: Modeling and implementation. ACM Transactions on Architecture and Code Optimization, 1(1):94-125, Mar. 2004.
32. G. S. Sohi and J. A. Butts. A static power model for architects. In Proceedings of the 33rd Annual ACM/IEEE International Symposium on Microarchitecture, pages 191-201, Dec. 2000.
33. V. Szekely, A. Poppe, A. Pahi, A. Csendes, G. Hajas, and M. Rencz. Electrothermal and logi-thermal simulation of VLSI designs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 5(3):258-269, Sept. 1997.
34. K. Torki and F. Ciontu. IC thermal map from digital and thermal simulations. In Proceedings of the 2002 International Workshop in THERMal Investigations of ICs and Systems, pages 303-308, Oct. 2002.
35. University of California, Berkeley. BSIM3v3.2.2 Manual, 1999.
36. S. Woo, M. Ohara, E. Torrie, J. Singh, and A. Gupta. The SPLASH-2 Programs: Characterization and Methodological Considerations. In International Symposium on Computer Architecture, pages 24-36, Santa Margherita Ligure, Italy, June 1995.
37. Y. Zhang, D. Parikh, K. Sankaranarayanan, K. Skadron, and M. R. Stan. Hotleakage: A temperature-aware model of subthreshold and gate leakage for architects. Technical Report CS-2003-05, Department of Computer Science, University of Virginia, Mar. 2003.