Predictions of CMOS compatible on-chip optical interconnect

International Workshop on System Level Interconnect Prediction, SLIP

Volumn , Issue , 2005, Pages 13-20

  Chen, Guoqing ^a   Chen, Hui ^a   Haurylau, Mikhail ^a   Nelson, Nicholas ^a   Fauchet, Philippe M ^a   Friedman, Eby G ^a   Albonesi, David ^b  

^a University of Rochester   (United States)

^b School of Operations Research and Industrial Engineering   (United States)

Author keywords

CMOS compatible; On chip; Optical interconnect; Trends

Indexed keywords

MICROPROCESSOR CHIPS; OPTICAL INTERCONNECTS;

ELECTRICAL INTERCONNECT; ON-CHIP OPTICAL INTERCONNECT; OPTICAL TECHNOLOGIES;

CMOS INTEGRATED CIRCUITS;

EID: 30944444424     PISSN: None     EISSN: 15445631     Source Type: Conference Proceeding    
DOI: 10.1145/1053355.1053360     Document Type: Conference Paper

References (28)

1. J. W. Goodman et al., "Optical Interconnects for VLSI Systems, " Proceedings of the IEEE, Vol. 72, No. 7, pp. 850-866, July 1984.
2. P. Kapur and K. C. Saraswat, "Comparisons Between Electrical and Optical Interconnects for On-Chip Signaling," Proceedings of the IEEE International International Interconnect Technology Conference, pp. 89-91, June 2002.
3. M. J. Kobrinsky et al., "On-Chip Optical Interconnects," Intel Technology Journal, Vol. 8, No. 2, pp. 129-141, May 2004.
4. The International Technology Roadmap for Semiconductors, Semiconductor Industry Association, California, 2003.
5. Y. I. Ismail and E. G. Friedman, "Sensitivity of Interconnect Delay to On-Chip Inductance." Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 403-406, May 2000.
6. V. Adler and Eby G. Friedman, "Repeater Design to Reduce Delay and Power in Resistive Interconnect," IEEE Transactions on Circuits and System II: Analog and Digital Signal Processing, Vol. 45, No. 5, pp. 607-616, May 1998.
7. P. Kapur, Scaling Induced Performance Challenges/Limitations of On-Chip Metal Interconnects and Comparisons with Optical Interconnects. Ph.D. Thesis, Stanford University, Stanford, California, 2002.
8. Y. I. Ismail and E. G. Friedman, "Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 8, No. 2, pp. 195-206, April 2000.
9. N. H. Mahmoud and Y. I. Ismail, "Accurate Rise Time and Overshoots Estimation in RLC Interconnects," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 477-480, May 2003.
10. G. Chen and E. G. Friedman, "Low Power Repeaters Driving RC Interconnect with Delay and Bandwidth Constraints," Proceedings of the IEEE International SOC Conference, pp. 335-339, September 2004.
11. G. P. Agrawal, Fiber-Optic Communication Systems. Wiley, New York, 1997.
12. C. A. Barrios, V. R. Almeida, and M. Lipson, "Low-Power-Consumption Short-Length and High-Modulation-Depth Silicon Electrooptic Modulator," Journal of Lightwave Technology, Vol. 21, No. 4, pp. 1089-1098, April 2003.
13. R. A. Soref and B. R. Bennett, "Electrooptical Effects in Silicon," IEEE Journal of Quantum Electronics, Vol. 23, No. 1, pp. 123-129, January 1987.
14. A. Liu et al., "A High-Speed Silicon Optical Modulator Based on a Metal-Oxide-Semiconductor Capacitor," Nature, Vol. 427, pp. 615-618, February 2004.
15. B. S. Cherkauer and E. G. Friedman, "A Unified Design Methodology for CMOS Tapered Buffers," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 3, No. 1, pp. 99-111, March 1995.
16. N. Hedenstierna and K. O. Jeppson, "CMOS Circuit Speed and Buffer Optimization," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 6, No. 2, pp. 270-281, March 1987.
17. T. Sakurai and A. R. Newton, "Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas," IEEE Journal of Solid-State Circuits, Vol. 25, No. 2, pp. 584-594, April 1990.
18. O. Boyraz and B. Jalali, "Demonstration of a Silicon Raman Laser," Optical Express, Vol. 12, No. 21, pp. 5269-5273, October 2004.
19. Y. A. Vlasov and S. J. McNab, "Losses in Single-Mode Silicon-On-Insulator Strip Waveguides and Bends," Optical Express, Vol. 12, No. 8, pp. 1622-1631, April 2004.
20. L. Eldada and L. W. Shacklette, "Advances in Polymer Integrated Optics," IEEE Journal of Selected Topics in Quantum Electronics. Vol. 6, No. 1, pp. 54-68, January/February 2000.
21. S. V. Averine, Y. C. Chan, and Y.L. Lam, "Geometry Optimization of Interdigitated Schottky-Barrier Metal-Semiconductor-Metal Photodiode Structures," Solid-State Electronics, Vol. 45, No. 3, pp. 441-446, March 2001.
22. J. Oh et al., "Interdigitated Ge p-i-n Photodetectors Fabricated on a Si Substrate Using Graded SiGe Buffer Layers," IEEE Journal of Quantum Electronics, Vol. 38, No. 9. pp. 1238-1241, September 2002.
23. D. Buca et al., "Metal-Germanium-Metal Ultrafast Infrared Detectors," Journal of Applied Physics, Vol. 92, No. 12, pp. 7599-7605, December 2002.
24. J. Oh, S. K. Banerjee, and J.C. Campbell, "Metal-Germanium-Metal Photodetectors on Heteroepitaxial Ge-on-Si with Amorphous Ge Schottky Barrier Enhancement Layers," IEEE Photonics Technology Letters, Vol. 15, No. 5, pp. 745-747, May 2003.
25. L. Pavesi and D. J. Lockwood, Silicon Photonics, Springer, New York, 2004.
26. S. Y. Chou and Y. Liu, "32 GHz Metal-Semiconductor-Metal Photodetector on Silicon," Applied Physics Letter, Vol. 61, No. 15, pp. 1760-1762, October 1992.
27. M. A. El-Moursy and E. G. Friedman, "Optimum Wire Sizing of RLC Interconnect with Repeaters,'' Proceedings of the IEEE Great Lakes Symposium on VLSI, pp. 27-32, April 2003.
28. R. Ho, K. W. Mai, and M. A. Horowitz, "The Future of Wires," Proceedings of the IEEE, Vol. 89, No. 4, pp. 490-504, April 2001.