The design of DEETM: A framework for dynamic energy efficiency and temperature management

Journal of Instruction-Level Parallelism

Volumn 3, Issue , 2001, Pages

  Huang, Michael ^a   Renau, Jose ^a   Yoo, Seung Moon ^a   Torrellas, Josep ^a  

^a University of Illinois at Urbana Champaign   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COOLING SYSTEMS; ELECTRIC BATTERIES; ENERGY EFFICIENCY; ENERGY UTILIZATION; MICROPROCESSOR CHIPS; OPTIMIZATION; REAL TIME SYSTEMS; SIGNAL ENCODING; TEMPERATURE CONTROL;

CHIP DESIGNS; FITTING TECHNIQUES; POWER MODES; TEMPERATURE MANAGEMENT;

ENERGY MANAGEMENT;

EID: 3242742096     PISSN: None     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (36)

1. T. Pering, T. Burd, and R. Brodersen, "The Simulation and Evaluation of Dynamic Voltage Scaling Algorithms," in International Symposium on Low Power Electronics and Design, pp. 76-81, August 1998.
2. H. Sanchez, B. Kuttanna, T. Olson, M. Alexander, G. Gerosa, R. Philip, and J. Alvarez, "Thermal Management System for High Performance PowerPC Microprocessors," in IEEE Computer Society International Conference, pp. 325-330, February 1997.
3. T. Halfhill, "Transmeta Breaks x86 Low-Power Barrier," Microprocessor Report, vol. 14, pp. 1,9-18, February 2000.
4. Intel, Pentium III Processor Mobile Module: Mobile Module Connector 2 (MMC-2) Featuring Intel SpeedStep Technology, 2000.
5. E. Rohou and M. Smith, "Dynamically Managing Processor Temperature and Power," in 2nd Workshop on Feedback-Directed Optimization, November 1999.
6. D. Albonesi, "Dynamic IPC/Clock Rate Optimization," in International Symposium on Computer Architecture, pp. 282-292, July 1998.
7. D. Brooks and M. Martonosi, "Adaptive Thermal Management for High-Performance Microprocessors," in Workshop on Complexity Effective Design, June 2000.
8. S. Manne, A. Klauser, and D. Grunwald, "Pipeline Gating: Speculation Control for Energy Reduction," in International Symposium on Computer Architecture, pp. 132-141, July 1998.
9. R. Gonzalez and M. Horowitz, "Energy Dissipation In General Purpose Microprocessors," IEEE Journal on Solid-State Circuits, vol. 31, pp. 1277-1284, September 1996.
10. K. Itoh, "Low Power Memory Design," in Low Power Design Methodologies, pp. 201-251, Kluwer Academic Publisher, 1996.
11. N. Vijaykrishnan, M. Kandemir, M. J. Irwin, H. S. Kim, and W. Ye, "Energy-Driven Integrated Hardware-Software Optimizations Using SimplePower," in International Symposium on Computer Architecture, pp. 95-106, June 2000.
12. K. Ghose and M. Kamble, "Reducing Power in Superscalar Processor Caches Using Subbanking, Multiple Line Buffers and Bit-Line Segmentation," in International Symposium on Low Power Electronics and Design, pp. 70-75, August 1999.
13. C.-L. Su and A. Despain, "Cache Design Trade-offs for Power and Performance Optimization: A Case Study," in International Symposium on Low Power Electronics and Design, pp. 63-68, April 1995.
14. J. Kin, M. Gupta, and W. Mangione-Smith, "The Filter Cache: An Energy Efficient Memory Structure," International Symposium on Microarchitecture, pp. 184-193, December 1997.
15. T. Juan, T. Lang, and J. Navarro, "Reducing TLB Power Requirements," in International Symposium on Low Power Electronics and Design, pp. 196-201, August 1997.
16. S. Ghiasi, J. Casmira, and D. Grunwald, "Using IPC Variation in Workloads with Externally Specified Rates to Reduce Power Consumption," in Workshop on Complexity-Effective Design, June 2000.
17. C.-H. Tsai, Temperature-Aware VLSI Design and Analysis. PhD thesis, Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, May 2000.
18. L. Benini, A. Bogliolo, S. Cavallucci, and B. Ricco, "Monitoring System Activity for OS-Directed Dynamic Power Management," in International Symposium on Low Power Electronics and Design, pp. 185-190, August 1998.
19. K. Itoh, "An Experimental 1Mb DRAM with On-Chip Voltage Limiter," in ISSCC Digest of Technical Papers, pp. 84-85, February 1981.
20. S.-M. Yoo, J. Renau, M. Huang, and J. Torrellas, "FlexRAM Architecture Design Parameters," Tech. Rep. CSRD-1584, Department of Computer Science, University of Illinois at Urbana-Champaign, October 2000. http://iacoma.cs.uiuc.edu/flexram/publications.html.
21. J. Veenstra and R. Fowler, "MINT: A Front End for Efficient Simulation of Shared-Memory Multiprocessors," in Second International Workshop on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems, pp. 201-207, January 1994.
22. V. Krishnan and J. Torrellas, "An Execution-Driven Framework for Fast and Accurate Simulation of Superscalar Processors," in International Conference on Parallel Architectures and Compilation Techniques, pp. 286-293, October 1998.
23. IBM Microelectronics, "Blue Logic SA-27E ASIC." http://www.chips.ibm.com/news/1999/sa27e, February 1999.
24. Y. Kang, W. Huang, S. Yoo, D. Keen, Z. Ge, V. Lam, P. Pattnaik, and J. Torrellas, "FlexRAM: Toward an Advanced Intelligent Memory System," in International Conference on Computer Design, pp. 192-201, October 1999.
25. J. Alvarez, H. Sanchez, G. Gerosa, and R. Countryman, "A Wide-Bandwidth Low-Voltage PLL for PowerPC Microprocessors," IEEE Journal on Solid-State Circuits, vol. 30, pp. 383-391, April 1995.
26. M. Kamble and K. Ghose, "Analytical Energy Dissipation Models for Low Power Caches," in International Symposium on Low Power Electronics and Design, pp. 143-148, August 1997.
27. J. Montanaro, R. Witek, K. Anne, A. Black, E. Cooper, D. Dobberpuhl, P. Donahue, J. Eno, W. Hoeppner, D. Kruckemyer, T. Lee, P. Lin, L. Madden, D. Murray, M. Pearce, S. Santhanam, K. Snyder, R. Stehpany, and S. Thierauf, "A 160-MHz, 32-b, 0.5-W CMOS RISC Microprocessor," IEEE Journal Solid State Circuits, vol. 31, pp. 1703-1714, November 1996.
28. S. Wilton and N. Jouppi, "CACTI: An Enhanced Cache Access and Cycle Time Model," IEEE Journal on Solid-State Circuits, vol. 31, pp. 677-688, May 1996.
29. N. Yeung, Y. Sutu, T. Su, E. Pak, C. Chao, S. Akki, D. Yau, and R. Lodenquai, "The Design of a 55SPECint92 RISC Processor under 2W," ISSCC Digest of Technical Papers, pp. 206-207, February 1994.
30. S. Sidiropoulos and M. Horowitz, "A Semidigital Dual Delay-Locked Loop," IEEE Journal on Solid-state Circuits, vol. 32, pp. 1683-1692, November 1997.
31. Intel, Microsoft and Toshiba, Advanced Configuration and Power Interface Specification, 1999.
32. J. Flinn and M. Satyanarayanan, "Energy-Aware Adaptation for Mobile Applications," in Symposium on Operating Systems Principles, pp. 48-63, December 1999.
33. J. Quinlan, C4.5-Programs for Machine Learning. Morgan Kaufmann, 1993.
34. R. Lawrence, G. Almasi, and H. Rushmeier, "A Scalable Parallel Algorithm for Self-Organizing Maps with Applications to Sparse Data Mining Problems," tech. rep., IBM, January 1998.
35. S. Altschul, W. Gish, W. Miller, E. Myers, and D. Lipman, "Basic Local Alignment Search Tool," Journal of Molecular Biology, vol. 215, pp. 403-410, October 1990.
36. Y. Fisher, Fractal Image Compression: Theory and Application. Springer Vertag, 1995.