Fast and accurate prediction of the steady-state throughput of multicore processors under thermal constraints

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 28, Issue 10, 2009, Pages 1559-1572

  Rao, Ravishankar ^a,b   Vrudhula, Sarma ^a  

^a Arizona State University   (United States)

^b SYNOPSYS INC   (United States)

Author keywords

Dynamic thermal management (DTM); Frequency scaling; Multicore processors; Power management; Throughput optimization.

Indexed keywords

DYNAMIC THERMAL MANAGEMENT (DTM); FREQUENCY SCALING; MULTICORE PROCESSORS; POWER MANAGEMENT; THROUGHPUT OPTIMIZATION.;

COMPUTATIONAL COMPLEXITY; ELECTRIC POWER MEASUREMENT; ELECTRIC POWER UTILIZATION; ENERGY MANAGEMENT; FLUIDIZED BED COMBUSTION; FORESTRY; HAND HELD COMPUTERS; SIMULATORS; SPACE RESEARCH; THROUGHPUT;

TEMPERATURE CONTROL;

EID: 70349752905     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2009.2026361     Document Type: Article

References (50)

1. Tile Processor Architecture: Technology Brief . [Online]. Available: http://www.tilera.com/pdf/ProductBrief-TileArchitecture-Web-v4.pdf
2. Intel Corp., Intel Core 2 Duo Processor E8000 and E7000 Series: Datasheet, Apr. 2008. [Online]. Available: http://download.intel.com/ design/processor/datashts/318732.pdf
3. AMD Athlon 64 X2 Dual-Core Processor Product Data Sheet, Adv. Micro Devices, Sunnyvale, CA, Jan. 2007.
4. J. Held, J. Bautista, and S. Koehl, From a Few Cores to Many: A Tera-Scale Computing Research Overview. Santa Clara, CA: Intel Corp., 2006. White Paper.
5. S. Borkar, "Thousand core chips-A technology perspective," in Proc. DAC, Jun. 2007, pp. 746-749.
6. D. Brooks and M. Martonosi, "Dynamic thermal management for high-performance microprocessors," in Proc. Int. Symp. HPCA, 2001, pp. 171-182.
7. K. Skadron, R. Stan, W. Huang, S. Veluswamy, K. Sankaranarayanan, and D. Tarjan, "Temperature-aware microarchitecture," in Proc. ISCA, 2003, pp. 2-13.
8. W. Liao, L. He, and K. M. Lepak, "Temperature and supply voltage aware performance and power modeling at microarchitecture level," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol.24, no.7, pp. 1042-1053, Jul. 2005.
9. W. Huang, M. R. Stan, K. Skadron, K. Sankaranarayanan, and S. Ghosh, "Hotspot: A compact thermal modeling method for CMOS VLSI systems," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.14, no.5, pp. 501-513, May 2006.
10. K. Skadron, M. R. Stan, K. Sankaranarayanan, W. Huang, S. Velusamy, and D. Tarjan, "Temperature-aware microarchitecture: Modeling and implementation," ACMTrans. Archit. Code Optim., vol.1, no.1, pp. 94-125, Mar. 2004.
11. J. Donald and M. Martonosi, "Techniques for multicore thermal management: Classification and new exploration," in Proc. ISCA, 2006, pp. 78-88.
12. S. Heo, K. Barr, and K. Asanovic, "Reducing power density through activity migration," in Proc. ISLPED, 2003, pp. 217-222.
13. M. Gomaa, M. D. Powell, and T. N. Vijaykumar, "Heat-and-run: Leveraging SMT and CMP to manage power density through the operating system," in Proc. ASPLOS, 2004, pp. 260-270.
14. P. Michaud, A. Seznec, D. Fetis, Y. Sazeides, and T. Constantinou, "A study of thread migration in temperature-constrained multicores," ACMTrans. Archit. Code Optim., vol.4, no.2, pp. 9-1-9-28, Jun. 2007.
15. P. Chaparro, J. Gonzlez, G. Magklis, Q. Cai, and A. Gonzlez, "Understanding the thermal implications of multi-core architectures," IEEE Trans. Parallel Distrib. Syst., vol.18, no.8, pp. 1055-1065, Aug. 2007.
16. Y. Li, B. Lee, D. Brooks, Z. Hu, and K. Skadron, "CMP design space exploration subject to physical constraints," in Proc. Int. Symp. HPCA, 2006, pp. 15-26.
17. C. Isci, A. Buyuktosunoglu, C.-Y. Cher, P. Bose, and M. Martonosi, "An analysis of efficient multi-core global power management policies: Maximizing performance for a given power budget," in Proc. Int. Symp. Microarch. (MICRO), 2006, pp. 347-358.
18. W. L. Bircher and L. K. John, "Analysis of dynamic power management on multi-core processors," in Proc. ICS, Jun. 2008, pp. 327-338.
19. A. Kayi, Y. Yao, T. El-Ghazawi, and G. Newby, "Experimental evaluation of emerging multi-core architectures," in Proc. IPDPS, Mar. 2007, pp. 1-6.
20. S. Murali, A. Mutapcic, D. Atienza, R. Gupta, S. Boyd, and G. D. Micheli, "Temperature-aware processor frequency assignment for MPSoCs using convex optimization," in Proc. Int. Conf. Hardw. Softw. Codesign (CODES), Oct. 2007, pp. 111-116.
21. C. Zhu, Z. Gu, L. Shang, R. P. Dick, and R. Joseph, "Three- dimensional chip-multiprocessor run-time thermal management," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol.27, no.8, pp. 1479-1492, Aug. 2008.
22. J. Donald and M. Martonosi, "Power efficiency for variation-tolerant multicore processors," in Proc. ISLPED, Aug. 2006, pp. 304-309.
23. R. Teodorescu and J. Torrellas, "Variation-aware application scheduling and power management for chip multiprocessors," in Proc. ISCA, Jun. 2008, pp. 363-374.
24. R. Kumar, K. I. Farkas, N. P. Jouppi, P. Ranganathan, and D. M. Tullsen, "Single-ISA heterogeneous multi-core architectures: The potential for processor power reduction," in Proc. Int. Symp. Microarch. (MICRO), Dec. 2003, pp. 81-92.
25. J. Yan and W. Zhang, "Hybrid multi-core architecture for boosting single- threaded performance," ACM SIGARCH Comput. Archit. News, vol.35, no.1, pp. 141-148, Mar. 2007.
26. J. W. Sheaffer, K. Skadron, and D. P. Luebke, "Studying thermal management for graphics-processor architectures," in Proc. ISPASS, Apr. 2005, pp. 54-65.
27. K. Stavrou and P. Trancoso, "Thermal-aware scheduling for future chip multiprocessors," EURASIP J. Embedded Syst., vol.2007, no.1, p. 40, Jan. 2007.
28. A. K. Coskun, T. S. Rosing, and K. Whisnant, "Temperature aware task scheduling for MPSoCs," in Proc. DATE Conf., Mar. 2007, pp. 1659-1664.
29. W. Wu, L. Jin, J. Yang, P. Liu, and S. X.-D. Tan, "Efficient power modeling and software thermal sensing for runtime temperature monitoring," ACM Trans. Des. Autom. Electron. Syst. (TODAES), vol.12, no.3, p. 25, Aug. 2007.
30. Y. Han, I. Koren, and C. M. Krishna, "Temptor: A lightweight runtime temperature monitoring tool using performance counters," in Proc. Workshop TACS, 2006. [Online]. Available: http://www.eecs.harvard.edu/~dbrooks/tacs06/
31. J. Srinivasan and S. V. Adve, "Predictive dynamic thermal management for multimedia applications," in Proc. ICS, Jun. 2003, pp. 109-120.
32. W. Lee, K. Patel, and M. Pedram, "Dynamic thermal management for MPEG-2 decoding," in Proc. ISLPED, Aug. 2006, pp. 316-321.
33. J. A. Darringer, "Multi-core design automation challenges," in Proc. DAC, Jun. 2007, pp. 760-764.
34. P. Michaud and Y. Sazeides, "ATMI: An analytical model of temperature in microprocessors," in Proc. WorkshopMOBS, Jun. 2007.
35. T. Heath, A. P. Centeno, P. George, L. Ramos, Y. Jaluria, and R. Bianchini, "Mercury and freon: Temperature emulation and management for server systems," in Proc. Int. Conf. ASPLOS, Oct. 2006, pp. 106-116.
36. D. Brooks, V. Tiwari, and M. Martonosi, "Wattch: A framework for architectural-level power analysis and optimizations," in Proc. ISCA, 2000, pp. 83-94.
37. A. Cohen, F. Finkelstein, A. Mendelson, R. Ronen, and D. Rudoy, "On estimating optimal performance of CPU dynamic thermal management," IEEE Comput. Archit. Lett., vol.2, no.1, p. 6, Jan. 2003.
38. R. Rao and S. Vrudhula, "Performance optimal processor throttling under thermal constraints," in Proc. Conf. CASES, Oct. 2007, pp. 257-266.
39. S. Cho and R. G. Melhelm, "Corollaries to Amdahl's law for energy," IEEE Comput. Archit. Lett., vol.7, no.1, pp. 25-28, Jan.- Jun. 2008.
40. J. Li and J. F. Martnez, "Power-performance considerations of parallel computing on chip multiprocessors," ACM Trans. Archit. Code Optim., vol.2, no.4, pp. 397-422, Dec. 2005.
41. D. Burger and T. Austin, "The simplescalar toolset," Univ. Wisconsin, Madison, Tech. Rep. 1342, Jun. 1997. ver. 2.0.
42. R. Rao, S. Vrudhula, C. Chakrabarti, and N. Chang, "An optimal analytical solution for processor speed control with thermal constraints," in Proc. ISLPED, Oct. 2006, pp. 292-297.
43. K. Skadron, T. Abdelzaher, and M. R. Stan, "Control-theoretic techniques and thermal-RC modeling for accurate and localized dynamic thermal management," in Proc. Int. Symp. HPCA, 2002, pp. 17-28.
44. P. Kongetira, K. Aingaran, and K. Olukotun, "Niagara: A 32-way multithreaded SPARC processor," IEEE Micro, vol.25, no.2, pp. 21-29, Mar. 2005.
45. NVIDIA CUDA Compute Unified Device Architecture Programming Guide, NVIDIA Corp., Santa Clara, CA, 2008.
46. S. Pope and D. Riddoch, "Virtualization and multicore x86 CPUs," Electronics Design, Strategy, News, Aug. 2008. [Online]. Available: http://www.edn.com/article/CA6584878.html
47. D. Field, D. Johnson, D. Mize, and R. Stober, "Scheduling to overcome the multi-core memory bandwidth bottleneck," Hewlett-Packard White Paper, Nov. 2007. [Online]. Available: http://www.platform.com/Products/ platform-lsf-family/platform-lsf/multicore- scheduling-whitepaper.pdf
48. M Curtis-Maury and J Dzierwa, "Online power-performance adaptation of multithreaded programs using hardware event-based prediction," in Proc. ICS, Jun. 2006, pp. 157-166.
49. W. Huang, K. Sankaranarayanan, R. J. Ribando, M. R. Stan, and K. Skadron, "An improved block-based thermal model in hotspot 4.0 with granularity considerations," in Proc. WDDD, Jun. 2007, pp. 1-10.
50. R. Rao and S. Vrudhula, "Efficient online computation of core speeds to maximize the throughput of thermally constrained multi-core processors," in Proc. ICCAD, Nov. 2008, pp. 537-542.